1. ECE 331 – Digital Systems Design Sequential Logic Circuits: FSM Design (Lecture #20)

2. ECE 331 - Digital Systems Design2 FSM Design: Procedure Understand specifications Derive state diagram Create state table Perform state minimization (if necessary) Encode states (state assignment) Create state-assigned table Select type of Flip-Flop to use Determine Flip-Flop input equations and FSM output equation(s) Draw logic diagram

3. ECE 331 - Digital Systems Design3 Moore Machines FSM Design

4. ECE 331 - Digital Systems Design4 Example: Design a FSM that detects a sequence of three or more consecutive ones on an input bit stream. The FSM should output a 1 when the sequence is detected, and a 0 otherwise. A circuit that detects the occurrence of a particular pattern on its input is referred to as a sequence detector. FSM Design (Moore)

5. ECE 331 - Digital Systems Design5 FSM Design: Example (Moore) Input: 0 1 1 1 0 1 0 1 1 0 1 1 1 0 1 … Output:0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 …

6. ECE 331 - Digital Systems Design6 FSM Design: Example (Moore) State Diagram

7. ECE 331 - Digital Systems Design7 FSM Design: Example (Moore) QAQA QBQB QA+QA+ QB+QB+ State Table

8. ECE 331 - Digital Systems Design8 FSM Design: Example (Moore) The choice of Flip-Flop determines the complexity of the combinational logic required in the design of the state machine. Each type of Flip-Flop has a unique characteristic equation. SR Flip-Flop  Q + = S + R'.Q D Flip-Flop  Q + = D JK Flip-Flop  Q + = J.Q' + K'.Q T Flip-Flop  Q + = T '.Q + T.Q'

9. ECE 331 - Digital Systems Design9 Synthesis using D Flip-Flops (Q + = D) FSM Design (Moore)

10. ECE 331 - Digital Systems Design10 FSM Design: Example (Moore) Flip-Flop Input D A D B Q + = D next stateflip-flop input QAQA QBQB QA+QA+ QB+QB+

11. ECE 331 - Digital Systems Design11 FSM Design: Example (Moore)

12. ECE 331 - Digital Systems Design12 FSM Design: Example (Moore) QAQA QBQB Q' B

13. ECE 331 - Digital Systems Design13 Synthesis using JK Flip-Flops (Q + = J.Q' + K'.Q) FSM Design (Moore)

14. ECE 331 - Digital Systems Design14 FSM Design: Example (Moore) + Excitation Table

15. ECE 331 - Digital Systems Design15 FSM Design: Example (Moore) Q + = J.Q' + K'.Q next stateflip-flop inputs QAQA QBQB QA+QA+ QB+QB+

16. ECE 331 - Digital Systems Design16 FSM Design: Example (Moore)

17. ECE 331 - Digital Systems Design17 FSM Design: Example (Moore) QAQA QBQB Q' B Q' A

18. ECE 331 - Digital Systems Design18 Example: Design a Finite State Machine (FSM) that meets the following specifications: This is another example of a sequence detector. 1. The circuit has one input, w, and one output, z. 2. All changes in the circuit occur on the positive edge of the clock. 3. The output z is equal to 1 if the pattern 101 is detected on the input w. Otherwise, the value of z is equal to 0. Overlapping sequences should not be detected. FSM Design (Moore)

19. ECE 331 - Digital Systems Design19 FSM Design: Example (Moore) Input (w): 0 0 0 1 0 1 0 1 1 0 1 1 0 1 1 … Output (z):0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 …

20. ECE 331 - Digital Systems Design20 FSM Design: Example (Moore) Start State End State State Diagram

21. ECE 331 - Digital Systems Design21 Example: Design a Finite State Machine (FSM) that meets the following specifications: This is another example of a sequence detector. 1. The circuit has one input, w, and one output, z. 2. All changes in the circuit occur on the positive edge of the clock. 3. The output z is equal to 1 if the pattern 101 is detected on the input w. Otherwise, the value of z is equal to 0. Overlapping sequences should be detected. FSM Design (Moore)

22. ECE 331 - Digital Systems Design22 FSM Design: Example (Moore) Input (w): 0 0 0 1 0 1 0 1 1 0 1 1 0 1 1 … Output (z):0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 …

23. ECE 331 - Digital Systems Design23 FSM Design: Example (Moore) Start State End State State Diagram

24. ECE 331 - Digital Systems Design24 Example: Design a Finite State Machine (FSM) that meets the following specifications: This is example of a sequence detector that can detect 2 sequences. 1. The circuit has one input, w, and one output, z. 2. All changes in the circuit occur on the positive edge of the clock. 3. The output z is equal to 1 if the pattern 110 or the pattern 010 is detected on the input w. Otherwise, the value of z is equal to 0. Overlapping sequences should be detected. FSM Design (Moore)

25. ECE 331 - Digital Systems Design25 FSM Design: Example (Moore) Input (w): 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1 … Output (z):0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 …

26. ECE 331 - Digital Systems Design26 FSM Design: Example (Moore) State Diagram

27. ECE 331 - Digital Systems Design27 Acknowledgments The slides used in this lecture were taken, with permission, from those provided by Pearson Prentice Hall for Digital Design (4 th Edition). They are the property of and are copyrighted by Pearson Education.