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PCI interface Clock Controller T-1000 TzDM TzPM JnPM PmSw J-1000 #0 J-1000 #7 Jn0 DM DtSw 4 x Com-1000 ServiceBus CPCI_BusApeChan DtBus GlobAddr PMAddress.

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Presentation on theme: "PCI interface Clock Controller T-1000 TzDM TzPM JnPM PmSw J-1000 #0 J-1000 #7 Jn0 DM DtSw 4 x Com-1000 ServiceBus CPCI_BusApeChan DtBus GlobAddr PMAddress."— Presentation transcript:

1 PCI interface Clock Controller T-1000 TzDM TzPM JnPM PmSw J-1000 #0 J-1000 #7 Jn0 DM DtSw 4 x Com-1000 ServiceBus CPCI_BusApeChan DtBus GlobAddr PMAddress Jn7 DM TzMcode JnMcode Jn0_Daad Jn7_Daad FastAPM SlowAPM /Sasha/ To/from Root X YZ Fig.1. Structure of the APEmille Processing Board TzModule JnModule_0JnModule_7

2 TzRF MicroCode Register ALU IF PC Com1000 control MX AGU Displ Load Reset SoftReset Z N GIF GCNB TzMcode DataBus GlobAddPMAddr ChCtrl TzHalt TzExc HaltRq OR SoftExc ALUexc AGUexc ……... Fig.2. T1000 architecture. MX /Sasha/

3 JnRF IFstack LOF LUT FILU Z N Fig.3. J1000 architecture (all commands except remote MTOJ ). JnDM control ….. JnDM_Data 64 bit 66MHz 64 bit 66MHz JnDM_Add GlobAdd OR Switch MicroCode Register JnMcode JnExc OR JnSoftExc FILU_exc Addr_exc ……... JnIF we3 we4 /Sasha/

4 JnRF LOF Fig.4. J1000 architecture (remote MTOJ). JnDM control ….. JnDM_Data 64 bit 8.1MHz JnDM_Add GlobAdd GlobTrans control …. RG MX 64 bit 8.1MHz 16 bit 33MHZ 16 bit 33MHZ Daad1 Daad0 MicroCode Register JnMcode /Sasha/

5 Fig.5. Com1000 architecture (remote transfer, 2x2x2 configuration). Trx control ChCtrl TsDt_Bus Jn0Daad0 Jn1Daad0 Jn2Daad0 Jn3Daad0 Jn4Daad0 Jn5Daad0 Jn6Daad0 Jn7Daad0 Jn0Daad1 Jn1Daad1 Jn2Daad1 Jn3Daad1 Jn4Daad1 Jn5Daad1 Jn6Daad1 Jn7Daad1 Crossbar Switch /Sasha/


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