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ITEC 325 Lecture 29 Memory(6). Review P2 assigned Exam 2 next Friday Demand paging –Page faults –TLB intro.

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Presentation on theme: "ITEC 325 Lecture 29 Memory(6). Review P2 assigned Exam 2 next Friday Demand paging –Page faults –TLB intro."— Presentation transcript:

1 ITEC 325 Lecture 29 Memory(6)

2 Review P2 assigned Exam 2 next Friday Demand paging –Page faults –TLB intro

3 Memory (6) Advantage of TLB When does TLB offer an advantage –When most of the page numbers the process refers to is in the TLB. –Determined by what is called as hit ratio – 0 <= hit ratio <= 1 –If hit ratio higher  greater chance of finding page in TLB –Example: Let memory access time be 100ns. Let TLB access time be 20ns. Hit ratio: 0.8. –What is the overhead of a lookup ?

4 Memory (6) Thrashing Consider this scenario: –The CPU is idle, lots of processes are waiting to execute. –The OS (to increase multiprocessing) loads the processes into the pages. –Now let us say, a process starts using more memory. Then it demands free frames in main memory. What if there are no free frames? Solution: steal from other process. What if the other process needs more frames? –Processes start page faulting – this causes the OS to think that the CPU is idle and it loads even more processes causes more thrashing. –Example: the.NET runtime optimization service. © Silberschatz and Galvin

5 Memory (6) Putting it All Together An example TLB holds 8 entries for a system with 32 virtual pages and 16 page frames.

6 Memory (6) Class exercise Consider a memory architecture that contains a TLB, an L1 cache, an L2 cache and main memory. 30%: hit rate of TLB. 90%: hit rate of L1 cache 95%: hit rate of L2 cache 10% page fault rate. Also accessing –TLB: 10 ns –L1 cache: 15 ns –L2 cache: 100 ns –Memory: 100 milliseconds. –Time to process a pagefault = 200 milliseconds What is the effective memory access time? (i.e., for any logical address that the CPU requests, how long does it take on average to read the data at that address?)

7 Memory (6) Segmentati on Paging is nice… but not the most efficient. –It is easy to implement, but does not consider any program semantics. It does not consider the locality of instructions. A more logical way to allocate memory non-contiguously: segmentation. –Memory-management scheme that supports user view of memory

8 User’s View of a Program

9 Logical View of Segmentation 1 3 2 4 1 4 2 3 user spacephysical memory space

10 Memory (6) Segmentatio n Architecture How will the logical to physical address mapping in segmentation differ from that of paging ? –Recall: Paging created fixed –sized pages. Segmentation creates arbitrary sized segments. –Does this create any difference between segmentation table and page table ? –Should the logical to physical memory translation architecture be different ?

11 Segmentation Hardware

12 Example of Segmentation © Silberschatz and Galvin

13 Memory (6) Segmentati on Architecture Segmentation is better over paging in protection too … –More logical protection –E.g., code segments can be shared, while data segments may not be set to shared. Protection –With each entry in segment table associate: validation bit = 0  illegal segment read/write/execute privileges Protection bits associated with segments; code sharing occurs at segment level

14 Memory (6) Paging Vs. Segmentati on Paging: –Easy to implement OS does not need to know about the logical structure of program at all. Page sizes are fixed – decision made by the OS when it is installed. –Address translation is faster. –BUT, Not logical like segmentation – hence program execution may be slower. Protection is not intuitive (it is blind).

15 Memory (6) But can they live together Paging with segmentation: –Divide every program into logical segments Physical to linear address. –Divide every segment into pages Linear to logical address. This is an architecture supported feature –The intel pentium supports pure paging as well as segmentation with paging.

16 Memory (6) Linux Linux uses only six segments: –User code and data – shared between all processes –Kernel code and data – unique to each process –A local descriptor segment – for process related segments –Task state segment – to store context switches. Uses a 3 –level paging scheme "Page table" is actually a three-level tree –Page Directory (root) –Page Tables (children) –Pages (grandchildren) Why 3 levels, why not just one level ? –What if you have 32 bit address space Size of page table for single level Size of page table for 3 levels.

17 Memory (6) Content Addressable Is addressed based on content and not a “memory address”. Used in networking components: switches, routers. Relationships between random access memory and content addressable memory:

18 Memory (6) Overview of CAM Source: (Foster, C. C., Content Addressable Parallel Processors, Van Nostrand Reinhold Company, 1976.)

19 Memory (6) The Intel 4 Pentium Memory System

20 Memory (6) Summary Segmentation Content addressable memory


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