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Work in Progress --- Not for Publication 1 ERD WG 3/20/09 Brussels IRC FxF Meeting ERD/ERM – IRC FxF Meeting Jim Hutchby & Mike Garner Brussels, Belgium.

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Presentation on theme: "Work in Progress --- Not for Publication 1 ERD WG 3/20/09 Brussels IRC FxF Meeting ERD/ERM – IRC FxF Meeting Jim Hutchby & Mike Garner Brussels, Belgium."— Presentation transcript:

1 Work in Progress --- Not for Publication 1 ERD WG 3/20/09 Brussels IRC FxF Meeting ERD/ERM – IRC FxF Meeting Jim Hutchby & Mike Garner Brussels, Belgium March 20, 2009 International Roadmap Committee Topics  Tech Transfer to PIDS/FEP, Etc.  Request to assess emerging research memory technologies

2 Work in Progress --- Not for Publication 2 ERD WG 3/20/09 Brussels IRC FxF Meeting Tech Transfer to PIDS/FEP ♦Introduction of technologies involving new materials requires ~12+ years from publication to manufacturing ♦The last 4 – 6 years of this 12+ year total R&D period is development related to PIDS/FEP. The first 6 – 8 years is research related to ERM/ERD.

3 ITRS 2009 IRC Meeting – March 20, 2009 Source: 2009 ITRS – ERD/ERM/PIDS/FEP Production Ramp-up Model &Technology Cycle Timing for III-V MOSFET Channel Replacement Materials Volume (Parts/Month) 1K 10K 100K Months -72 1M 10M 100M Alpha Tool 024 -48 Development Production Beta Tool Product Tool First Conf. Papers 1 st 2Cos. Reach Product Volume (Wafers/Month) 2 20 200 2K 20K 200K -24 Research -96 Transfer to PIDS/FEP (2009–2013) 201920172015201320112021

4 SRC/File name/ 4 Transistor1923 – 19391947-481951AT&T1951-52 - TI, AT&T, GE, HP. Motorola DoD Integrated Circuit 1944 – 1957 (micromodule program) 1958–R.Noyce, J.Kilby 1961U.S. AirForce 1961 TI, FairchildNASA, DoD Data Processing 1889Hollerith1890U.S. Census Bureau 1896 – Tabulating Machine Co (from 1917 – IBM) U.S. Census Bureau 1946 -Eckert- Mauchly Co (1951 –Remington) U.S. Census Bureau Computer1841 (Babbage) 1889 Hollerith 1945 - ENIAC1946-1951DoD 1951 IBMDoD Disruptive Technologies in Electronics

5 5 Time Gaps Transfer of Knowledge Prototype built (Disruptive Technology) Entrant Co formed Market production (Established Technology) T1~ 20years ~10years T2T3 Solid State Diode T1 26 (1874-1900) T2 7 (1900-1907) T3 6 (1907-1913) Learning Period 13 years Vacuum Tube T1 20 (1884-1904) T2 9 (1904-1913) T3 6 (1913-1919) Learning Period 15 years Transistor T1 25 (1923-1948) T2 6 (1948-1954) T3 5 (1954-1959) Learning period 11years Integrated Circuit T1 17 (1942-1959) T2 3 (1959-1961) T3 5(1961-1966) Learning Period 8 years ‘Research Curve’ Human Carrier Sponsor1st Customer Example: Solid State Rectifier Enabling Background exists

6 6 Development Cycle Times for Sample IC Technologies Year InitiallyYear ImplementedLag Tool or Technology DevelopedIn ProductionTime Silicon Epitaxy1960-6119644 APCVD Silicon Nitride19651967-682 Ion Implant196919734 TiW Metalization1969-701975-776 Schottky TTL19701974-754 Charge-Coupled Device1970198111 Reactive Ion Etch1975-7619805 Polysilicon Emitter19761984-858 Refractory Gate197619837 SOI (via Ion Implant)1978198911 Trench Capacitor197919867 Silicide197819857 Lightly-Doped Drain198019866 Average6 years Source: Graydon Larrabee of Texas Instruments

7 7 Study of R&D Latency for a few Semiconductor Technologies  CMOS  Giant Magnetoresistance (GMR)  Copper Interconnect  193 nm photoresist  Magnetic RAM  EUV lithography Method. We used the following parameters: 1) The first publication on a given technology that appeared in the Science Citation Index database 2) The number of refereed articles in technical journals by year (Science Citation Index database) 3) The year of first production for a given technology

8 8 CMOS 1969 – 1 st publication 1972 – Toshiba CMOS calculator IC 1982 – Intel 80286 CMOS microprocessor 1983 – 1 st CMOS DRAM ( Intel) 1984 – Motorola 68020 CMOS microprocessor 1987 –CMOS at AMD 1981 – National NSC800 CMOS microprocessor 12 years

9 9 Giant Magnetoresistance (GMR) 1988 - discovery of GMR effect 1997- 1 st hard disk product using GMR heads ( IBM) 1992 – MRAM concept 9 years

10 10 Copper Interconnect 2000 – AMD x86 Cu- based microprocessor 1998 - Power PC 750 microprocessor ( IBM) 1986 – 1 st publication 12 years

11 11 193 nm photoresist 2001- 3M debuts 193nm photoresist chemicals 1989 – 1 st publication 12 years

12 12 Magnetic RAM 1992 – 1 st publication 12 years 2004- 1 st MRAM product projected ( IBM/Infineon)

13 Work in Progress --- Not for Publication 13 ERD WG 3/20/09 Brussels IRC FxF Meeting New Technology Introduction Events Strained Silicon Example –First Technology Paper: 1991, 1994 –Addition to ITRS Roadmap: ~2001 –Alpha Tool: TBD –ITRS Production: 2003 (12 years) –Technology Life: 3+ Generations High κ (HfO 2 ) Example –First Technology Paper: 1972 –Industry Interest ~1990 –Addition to ITRS Roadmap: 1997 –Alpha Tool: TBD –ITRS Production: 2010 (38 years) –Technology Life: 3+ Generations

14 Beyond CMOS CTSG Feb. 3, 2009 Work in Progress: Not for Distribution 14 Conclusions The average time from first research paper on a technology typically using a new material to its’ first commercial production is about 12 years. ♦ Research must have been in progress at least a few years before the first publication ♦ Development of technology leading to first product is 4 – 6 years, based on the time gaps study [(T2+T3)/(T1+T2+t3) = 1/3 to 1/2] applied to the current study.

15 Work in Progress --- Not for Publication 15 ERD WG 3/20/09 Brussels IRC FxF Meeting ERD ITWG Emerging Research Devices Working Group Proposal for Assessing Technology Options for Emerging Research Memory Devices Jim Hutchby & Mike Garner Friday March 20, 2009

16 Work in Progress --- Not for Publication 16 ERD WG 3/20/09 Brussels IRC FxF Meeting Objective of IRC/ERD/ERM discussion of this request from Samsung, Hynix, and Micron ERD/ERM is seeking IRC guidance on whether we should conduct a review and assessment of emerging research memory technologies with the goal of recommending those most promising for detailed roadmapping and accelerated research. ♦Assess technology capability of being scaled beyond the 15nm node. ♦Identify precompetitive research required for top candidates to scale beyond the 15nm node ♦Process will be completed in April 2010 with an oral report to the IRC in the Spring ITRS Meeting followed by a written report/recommendation to the IRC.

17 Work in Progress --- Not for Publication 17 ERD WG 3/20/09 Brussels IRC FxF Meeting Assessment of Promising Emerging Memory Devices Samsung, Hynix, and Micron proposed that the ERD/ERM identify memory technologies needing more focused support Proposal: ERD & ERM hold a workshop in April 2010 to review and assess emerging research memory devices –Goal: Identify emerging research memory technologies that merit more detailed roadmapping and more focused research. –Process: Same Process as the Logic Assessment in 2008 Champions present Pros, Cons and research needed for technology Friendly critic presents balanced assessment White paper prepared on each memory and circulated prior to the meeting Face to Face Presentations & Discussion Voting on Promising Technology Identify Critical Research Needed

18 Work in Progress --- Not for Publication 18 ERD WG 2/26/2009 Straw Candidate Emerging Research Memory Technologies  Capacitive Memory  FeFET Memory  Resistive Memory  Nanoelectromechanical  STT MRAM  Thermal PCM  FUSE/Anti-FUSE  Nanowire PCM  Electrochemical Memory  Cation migration  Anion migration  Electronic Effects Memory  Charge trapping  Mott Transition  FE barrier effects  Macromolecular Memory  Molecular Memory

19 Work in Progress --- Not for Publication 19 ERD WG 2/26/2009 DRAFT GOAL With the goal of providing input to resource allocation decisions, ERD/ERM WGs will conduct an in-depth review and assessment of specific emerging research memory devices to highlight the most promising device technologies for detailed roadmapping and acceleration of pre-competitive*research and development. (*Pre-competitive refers to those technologies capable of being scaled beyond the 15nm node.)

20 Work in Progress --- Not for Publication 20 ERD WG 2/26/2009 DRAFT SCOPE The scope of the review of emerging research memory technologies will assess scalability beyond the 15nm node. –Identify precompetitive research needed to enable scaling beyond the 15nm node. –Assessment will encompass both stand-alone and, where different, embedded emerging research memory technologies.

21 Work in Progress --- Not for Publication 21 ERD WG 2/26/2009 Draft Timetable 1. Develop/decide process, milestones, timelineJuly 12, 2009 2.Develop invitation to advocates/proponents & friendly critics  Introduction  Potential of technology – fundamental limits  Barriers – Fundamental vs. technological/engineering  Evaluation Criteria  Definition of specific emerging research memory devices for roadmapping  Readiness in 10 - 15 years July 31 3.Identify  Major emerging research memory device candidates  Strong technical proponent and friendly critic teams and their leaders  Knowledgeable ERD/ERM mentor for each proponent team  Key questions to be addressed by the teams  Background materials for each technical candidate July 31 4.Issue invitations to team leaders, friendly critics, and ERD/ERM mentors and obtain their commitments Sept. 15 5.Obtain a white per & background materials from each candidate technology proponent team for ERD/ERM WG review Jan. 15, 2010 6.ERD/ERM WG review candidate emerging research memory devices candidates based on white papers & identify key questions using a formal process prior to Spring Europe FxF meeting. Mar. 15, 2010 7.Conduct a FxF review of categories with each proponent & friendly critic making a presentation April yy, 2010 Spring FXF Mtg. 8.On second day of ERD FxF meeting, discuss/decide ERD/ERM WG’s prioritized recommendation of narrowed emerging research memory devices options. This will include selection of specific devices for roadmapping within the recommended option April yy+1,2010 Spring FXF Mtg. 9.Write & submit report on ERD/ERM WG’s recommendationsMay 31, 2010

22 Work in Progress --- Not for Publication 22 ERD WG 3/20/09 Brussels IRC FxF Meeting Proposed ERD/ERM WG Process for Assessing Candidate Emerging Research Memory Device Technology Options  Develop/decide process, milestones, timeline  Develop invitation to advocates & opponents  Introduction  Potential of technology – fundamental limits  Barriers – Fundamental vs. technological/engineering  Evaluation Criteria / Benchmark memory technology  Definition of maturing, high potential specific devices for roadmapping  Readiness in ~ 5 - 10 years

23 Work in Progress --- Not for Publication 23 ERD WG 3/20/09 Brussels IRC FxF Meeting Proposed ERD/ERM WG Process for Assessing Candidate Emerging Research Memory Device Technology Options  Identify  Major emerging research memory technology candidates  Strong technical proponent and opponent teams and their leaders  Knowledgeable ERD/ERM mentor for each proponent team  Key questions to be addressed by the teams  Background materials for each technical candidate  Issue invitations to team leaders and obtain their commitments  Obtain a white paper & background materials from each candidate technology proponent team for ERD/ERM review

24 Work in Progress --- Not for Publication 24 ERD WG 2/26/2009 REDO THIS SLIDE

25 Work in Progress --- Not for Publication 25 ERD WG 2/26/2009

26 Work in Progress --- Not for Publication 26 ERD WG 3/20/09 Brussels IRC FxF Meeting Proposed ERD/ERM WG Process for Assessing Candidate Emerging Research Memory Device Technology Options  ERD/ERM WG rate and prioritize candidate emerging research memory technologies using a formal process prior to FxF meeting.  Conduct a FxF review of categories with each proponent & opponent team making a presentation  On second day of ERD/ERM FxF meeting, discuss/decide ERD/ERM’s recommendation of most promising emerging research memory technology options.  Write & submit report to the IRC on ERD/ERM WG’s recommendations

27 Work in Progress --- Not for Publication 27 ERD WG 2/26/2009 BACKGROUND SLIDES

28 Work in Progress --- Not for Publication 28 ERD WG 2/26/2009 Proposed ERD/ERM WG Process for Assessing Candidate Emerging Research Memory Device Technology Options  Develop/decide process, milestones, timeline  Identify  Major memory technology candidates  Strong technical proponent and friendly critic teams and their leaders  Knowledgeable ERD/ERM mentor for each proponent team  Key questions to be addressed by the teams  Background materials for each technical candidate  Develop invitation to proponents & friendly critics  Introduction  Potential of technology – fundamental limits  Barriers – Fundamental vs. technological/engineering  Evaluation Criteria  Definition of specific devices for roadmapping  Readiness in 10-15 years

29 Work in Progress --- Not for Publication 29 ERD WG 2/26/2009 Proposed ERD/ERM WG Process for Assessing Candidate Emerging Research Memory Device Technology Options  Issue invitations to proponent and friendly critic team leaders and obtain their commitments  Identify ERD/ERM Mentors – 1 per candidate memory technology  Obtain a white paper & background materials from each candidate technology proponent team for ERD/ERM review  ERD/ERM WG review candidate emerging research memory technologies using a formal process prior to FxF meeting to identify questions to be addressed in FxF meeting.

30 Work in Progress --- Not for Publication 30 ERD WG 2/26/2009 Proposed ERD/ERM WG Process for Assessing Candidate Emerging Research Memory Device Technology Options  Conduct a FxF review of categories with each proponent & friendly critic team making a presentation  On second day of ERD/ERM FxF meeting, discuss/decide ERD/ERM’s recommendation of most promising emerging research memory technology options. Mentors will lead the discussion of their candidate technology  Write & submit report to the IRC on ERD/ERM WG’s recommendations

31 Work in Progress --- Not for Publication 31 ERD WG 2/26/2009 Decision Making & Majority Voting Scheme  Each member of ERD WG will be given a maximum of X votes to use in voting for their top X choices among the candidate technologies (Majority Voting scheme)  ERD/ERM WG members present in the FIRST DAY Workshop & the SECOND DAY meeting will be eligible to vote at SECOND DAY meeting, based on their personal technical judgment, independent of their corporate affiliation or regional representation,  Only 0 or 1 vote can be cast for any candidate technology  Member does not have to use all X votes, but cannot use more than X votes.  All members can participate in the straw vote.  The Candidate Technologies will be ordered according to which received the largest number of votes.  Consensus approval will be our goal, but a 75% affirmative vote will be required as a minimum. This is what is meant by the term approximate consensus. REDO THIS SLIDE

32 Work in Progress --- Not for Publication 32 ERD WG 2/26/2009 ERD “Beyond CMOS” Technology Selection Mtg Agenda – SECOND DAY 9:20Review Process for selecting beyond CMOS emerging technologies 9:45Discuss Technologies 9:45NEMS Switch Technology 10:05Spin Torque Transfer Technology 10:25Carbon-based Nanoelectronics 10:45Break 11:00Atomic Switch / Electrochemical Metal Switch 11:20Collective Spin Devices (including M-QCA) 11:40Single Electron Transistors 12:00CMOL and FPNI REDO THIS SLIDE

33 Work in Progress --- Not for Publication 33 ERD WG 2/26/2009 ERD “Beyond CMOS” Technology Selection Mtg Agenda – SECOND DAY (Cont’d) 12:50Preliminary vote on technologies – Majority voting process 1:00Discuss preliminary results 1:45Second vote on technologies 2:00Discuss the leading technologies resulting from vote 2:30Final vote on the leading technology(ies) to determine if we have approximate consensus (75% of those voting) to recommend one or more for roadmapping and enhanced engineering development 2:45 Decide next steps in roadmapping the chosen technologies REDO THIS SLIDE


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