1. 06/09/5806/09/5806/09/5806/09/58 1 ECE-590 Introduction to VHDL Prof. K. J. Hintz Department of Electrical and Computer Engineering http://fame.gmu.edu/~khintz (with hyperlink to ECE-590 vhdl near bottom of page)

2. 06/09/5806/09/5806/09/5806/09/58 2 RASSP  Many of materials used in this course come from ARPA RASSP Program and are copyright  Rapid Prototyping of Application Specific Signal Processors Program  http://rassp.scra.org  Rest of materials are copyright K. J. Hintz

3. 06/09/5806/09/5806/09/5806/09/58 3 Tools for Homework  Mentor Graphics QuickVHDL, 10 license  Received, but not yet installed on  site.gmu.edu  bass.gmu.edu  bzy.gmu.edu  IEEE VHDL Tutorial  Backordered, due mid-February  Cypress Semiconductor (Warp release 4.1)  PC-based, Windows 3.1 with win32s extension  $99 with textbook  Oriented towards PLD & FPGA devices  VHDL simulator

4. 06/09/5806/09/5806/09/5806/09/58 4 Basic VHDL RASSP Education & Facilitation Module 10 Version 1.6 Copyright  1995, 1996 RASSP E&F All rights reserved. This information is copyrighted by the RASSP E&F Program and may only be used for non-commercial educational purposes. Any other use of this information without the express written permission of the RASSP E&F Program is prohibited. All information contained herein may be duplicated for non- commercial educational use provided this copyright notice is included. No warranty of any kind is provided or implied, nor is any liability accepted regardless of use. FEEDBACK: The RASSP E&F Program welcomes and encourages any feedback that you may have including any changes that you may make to improve or update the material. You can contact us at feedback@rassp.scra.org or http://rassp.scra.org/module-request/FEEDBACK/feedback-on-modules.html RASSP E&F SCRA GT UVA Raytheon UCinc EIT ADL Copyright  1995, 1996 RASSP E&F

5. 06/09/5806/09/5806/09/5806/09/58 5 Motivation  Digital systems have become large and complex  Breadboard and prototypes are too costly for demonstrating complex system performance  Need analysis and simulation of hardware and software  There is a shift from structural to behavioral design  Different models of the same system are used at different stages and by different designers, resulting in  Possibility of loss of information  Difficulties or misunderstandings caused by inconsistencies between different models  Need to use different tools for different models  Redesign of digital systems costs $ 5-10 billions annually in US alone Copyright  1995, 1996 RASSP E&F

6. 06/09/5806/09/5806/09/5806/09/58 6 Need for VHDL  Need a unified environment  Need capability for transition from system-level model to the final implementation in a step-wise manner  Need an integrated system-level analysis and design  Need to incorporate performance, dependability, and functional modeling capability at all hierarchies of the design  Need to have power and flexibility to model digital systems at many different levels of description  Support “mixed” simulation at different levels of abstraction, representation, and interpretation with an ability for step-wise refinement Copyright  1995, 1996 RASSP E&F

7. 06/09/5806/09/5806/09/5806/09/58 7 Different Models  Behavioral model: Describes the function and timing of hardware independent of any specific implementation  Can exist at multiple levels of abstraction, depending on the granularity of the timing and the data types that are used in the functional description  Data flow, procedural and structural constructs may be used to express behavior  Structural model: Represents a system in terms of the interconnections of a set of components  Components are described structurally or behaviorally, with interfaces between structural and behavioral-level models  Physical model: Specifies the relationship between the component model and the physical packaging of the component. Copyright  1995, 1996 RASSP E&F

8. 06/09/5806/09/5806/09/5806/09/58 8 RASSP Roadmap VHDL SYSTEM DEF. FUNCTION DESIGN HW & SW PART. HW DESIGN SW DESIGN HW FAB SW CODE INTEG. & TEST VIRTUAL PROTOTYPE RASSP DESIGN LIBRARIES AND DATABASE Primarily software Primarily hardware HW & SW CODESIGN Copyright  1995, 1996 RASSP E&F

9. 06/09/5806/09/5806/09/5806/09/58 9 Lecture Goals  Introduce VHDL Concept and Motivation for VHDL  Introduce the VHDL Hierarchy and Alternative Architectures Model  Start Defining VHDL Syntax Copyright  1995, 1996 RASSP E&F

10. 06/09/5806/09/5806/09/5806/09/58 10 Outline  VHDL Background/History  VHDL Design Example  VHDL Model Components  Entity Declarations  Architecture Descriptions  Basic Syntax and Lexigraphical Conventions Copyright  1997, KJH

11. 06/09/5806/09/5806/09/5806/09/58 11 Reasons for Using VHDL  VHDL is an international IEEE standard specification language (IEEE 1076-1993) for describing digital hardware used by industry worldwide  VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language  VHDL enables hardware modeling from the gate to system level  VHDL provides a mechanism for digital design and reusable design documentation Copyright  1995, 1996 RASSP E&F

12. 06/09/5806/09/5806/09/5806/09/58 12 VHDL’s History  Very High Speed Integrated Circuit (VHSIC) Program  Launched in 1980  Aggressive effort to advance state of the art  Object was to achieve significant gains in VLSI technology  Need for common descriptive language  $17 Million for direct VHDL development  $16 Million for VHDL design tools  Woods Hole Workshop  Held in June 1981 in Massachusetts  Discussion of VHSIC goals  Comprised of members of industry, government, and academia Copyright  1995, 1996 RASSP E&F

13. 06/09/5806/09/5806/09/5806/09/58 13 VHDL’s History (Cont.)  In July 1983, a team of Intermetrics, IBM and Texas Instruments were awarded a contract to develop VHDL  In August 1985, the final version of the language under government contract was released: VHDL Version 7.2  In December 1987, VHDL became IEEE Standard 1076-1987 and in 1988 an ANSI standard  In September 1993, VHDL was restandardized to clarify and enhance the language  VHDL has been accepted as a Draft International Standard by the IEC Copyright  1995, 1996 RASSP E&F

14. 06/09/5806/09/5806/09/5806/09/58 14 Gajski and Kuhn’s Y Chart Physical/Geom etry Structur al Behavior al Process or Hardware Modules ALUs, Registers Gates, FFs Transisto rs Syste ms Algorith ms Register Transfer Logi c Transfer Functions Architectur al Algorithm ic Functional Block Logi c Circui t Rectangl es Cell, Module Plans Floor Plans Cluste rs Physical Partitions Copyright  1995, 1996 RASSP E&F

15. 06/09/5806/09/5806/09/5806/09/58 15 Additional Benefits of VHDL  Allows for various design methodologies  Provides technology independence  Describes a wide variety of digital hardware  Eases communication through standard language  Allows for better design management  Provides a flexible design language  Has given rise to derivative standards :  WAVES, VITAL, Analog VHDL Copyright  1995, 1996 RASSP E&F

16. 06/09/5806/09/5806/09/5806/09/58 16 Putting It All Together Generic s Ports Entity Architectur e Concurren t Statement s Process Sequential Statements Concurren t Statement s Package Copyright  1995, 1996 RASSP E&F

17. 06/09/5806/09/5806/09/5806/09/58 17 VHDL Design Example  Problem: Design a single bit half adder with carry and enable  Specifications  Inputs and outputs are each one bit  When enable is high, result gets x plus y  When enable is high, carry gets any carry of x plus y  Outputs are zero when enable input is low x y enable carry result Half Adder Copyright  1995, 1996 RASSP E&F

18. 06/09/5806/09/5806/09/5806/09/58 18 VHDL Design Example Entity Declaration  As a first step, the entity declaration describes the interface of the component  input and output ports are declared x y enable carry result Half Adder ENTITY half_adder IS PORT( x, y, enable: IN BIT; carry, result: OUT BIT); END half_adder; Copyright  1995, 1996 RASSP E&F

19. 06/09/5806/09/5806/09/5806/09/58 19 VHDL Design Example Behavioral Specification  A high level description can be used to describe the function of the adder l The model can then be simulated to verify correct functionality of the component ARCHITECTURE half_adder_a OF half_adder IS BEGIN PROCESS (x, y, enable) BEGIN IF enable = ‘1’ THEN result <= x XOR y; carry <= x AND y; ELSE carry <= ‘0’; result <= ‘0’; END IF; END PROCESS; END half_adder_a; Copyright  1995, 1996 RASSP E&F

20. 06/09/5806/09/5806/09/5806/09/58 20 VHDL Design Example Data Flow Specification  A second method is to use logic equations to develop a data flow description l Again, the model can be simulated at this level to confirm the logic equations ARCHITECTURE half_adder_b OF half_adder IS BEGIN carry <= enable AND (x AND y); result <= enable AND (x XOR y); END half_adder_b; Copyright  1995, 1996 RASSP E&F

21. 06/09/5806/09/5806/09/5806/09/58 21 VHDL Design Example Structural Specification  As a third method, a structural description can be created from predescribed components l These gates can be pulled from a library of parts x y enable carry result Copyright  1995, 1996 RASSP E&F

22. 06/09/5806/09/5806/09/5806/09/58 22 VHDL Design Example Structural Specification (Cont.) ARCHITECTURE half_adder_c OF half_adder IS COMPONENT and2 PORT (in0, in1 : IN BIT; out0 : OUT BIT); END COMPONENT; COMPONENT and3 PORT (in0, in1, in2 : IN BIT; out0 : OUT BIT); END COMPONENT; COMPONENT xor2 PORT (in0, in1 : IN BIT; out0 : OUT BIT); END COMPONENT; FOR ALL : and2 USE ENTITY gate_lib.and2_Nty(and2_a); FOR ALL : and3 USE ENTITY gate_lib.and3_Nty(and3_a); FOR ALL : xor2 USE ENTITY gate_lib.xor2_Nty(xor2_a); -- description is continued on next slide Copyright  1995, 1996 RASSP E&F

23. 06/09/5806/09/5806/09/5806/09/58 23 VHDL Design Example Structural Specification (cont.) -- continuing half_adder_c description SIGNAL xor_res : BIT; -- internal signal -- Note that other signals are already declared in entity BEGIN A0 : and2 PORT MAP (enable, xor_res, result); A1 : and3 PORT MAP (x, y, enable, carry); X0 : xor2 PORT MAP (x, y, xor_res); END half_adder_c; Copyright  1995, 1996 RASSP E&F

24. 06/09/5806/09/5806/09/5806/09/58 24 VHDL Model Components  A complete VHDL component description requires a VHDL entity and a VHDL architecture  The entity defines a component’s interface  The architecture defines a component’s function  Several alternative architectures may be developed for use with the same entity  Three areas of description for a VHDL component:  Structural descriptions  Behavioral descriptions  Timing and delay descriptions (kjh: cover this at a later time) Copyright  1995, 1996 RASSP E&F

25. 06/09/5806/09/5806/09/5806/09/58 25 VHDL Model Components (cont.)  Fundamental unit for component behavior description is the process  Processes may be explicitly or implicitly defined and are packaged in architectures  Primary communication mechanism is the signal  Process executions result in new values being assigned to signals which are then accessible to other processes  Similarly, a signal may be accessed by a process in another architecture by connecting the signal to ports in the the entities associated with the two architectures  Example signal assignment statement : Output <= My_id + 10; Copyright  1995, 1996 RASSP E&F

26. 06/09/5806/09/5806/09/5806/09/58 26 Entity Declarations  The primary purpose of the entity is to declare the signals in the component’s interface  The interface signals are listed in the PORT clause  In this respect, the entity is akin to the schematic symbol for the component  Additional entity clauses and statements will be introduced later in this and subsequent modules x y enable carry result Half Adder ENTITY half_adder IS GENERIC(prop_delay : TIME := 10 ns); PORT( x, y, enable : IN BIT; carry, result : OUT BIT); END half_adder; Copyright  1995, 1996 RASSP E&F

27. 06/09/5806/09/5806/09/5806/09/58 27 Entity Declarations Port Clause  PORT clause declares the interface signals of the object to the outside world  Three parts of the PORT clause  Name  Mode  Data type  Example PORT clause:  Note port signals (i.e. ‘ports’) of the same mode and type or subtype may be declared on the same line PORT (signal_name : mode data_type); PORT ( input : IN BIT_VECTOR(3 DOWNTO 0); ready, output : OUT BIT ); PORT ( input : IN BIT_VECTOR(3 DOWNTO 0); ready, output : OUT BIT ); Copyright  1995, 1996 RASSP E&F

28. 06/09/5806/09/5806/09/5806/09/58 28 Entity Declarations Port Clause (cont.)  The port mode of the interface describes the direction in which data travels with respect to the component  The five available port modes are:  In - data comes in this port and can only be read  Out - data travels out this port  Buffer - data may travel in either direction, but only one signal driver may be on at any one time  Inout - data may travel in either direction with any number of active drivers allowed; requires a Bus Resolution Function  Linkage - direction of data flow is unknown Copyright  1995, 1996 RASSP E&F

29. 06/09/5806/09/5806/09/5806/09/58 29 Entity Declarations Generic Clause  Generics may be used for readability, maintenance and configuration  Generic clause syntax :  If optional default_value missing in generic clause declaration, it must be present when component is to be used (i.e. instantiated)  Generic clause example :  The generic My_ID, with a default value of 37, can be referenced by any architecture of the entity with this generic clause  The default can be overridden at component instantiation GENERIC (generic_name : type [:= default_value]); GENERIC (My_ID : INTEGER := 37); Copyright  1995, 1996 RASSP E&F

30. 06/09/5806/09/5806/09/5806/09/58 30 Architecture Bodies  Describe the operation of the component  Consist of two parts :  Declarative part -- includes necessary declarations, e.g. :  type declarations, signal declarations, component declarations, subprogram declarations  Statement part -- includes statements that describe organization and/or functional operation of component, e.g. :  concurrent signal assignment statements, process statements, component instantiation statements ARCHITECTURE half_adder_d OF half_adder IS SIGNAL xor_res : BIT; -- architecture declarative part BEGIN -- begins architecture statement part carry <= enable AND (x AND y); result <= enable AND xor_res; xor_res <= x XOR y; END half_adder_d; Copyright  1995, 1996 RASSP E&F

31. 06/09/5806/09/5806/09/5806/09/58 31 Structural Descriptions  Pre-defined VHDL components are ‘instantiated’ and connected together  Structural descriptions may connect simple gates or complex, abstract components  Mechanisms for supporting hierarchical description  Mechanisms for describing highly repetitive structures easily Input Output Behavioral Entity Copyright  1995, 1996 RASSP E&F

32. 06/09/5806/09/5806/09/5806/09/58 32 Behavioral Descriptions  VHDL provides two styles of describing component behavior  Data Flow: concurrent signal assignment statements  Behavioral: processes used to describe complex behavior by means of high-level language constructs  variables, loops, if-then-else statements, etc.  A behavioral model may bear little resemblance to system implementation  Structure not necessarily implied Input Output Behavioral Descriptio n Copyright  1995, 1996 RASSP E&F

33. 06/09/5806/09/5806/09/5806/09/58 33 Lexical Elements of VHDL  Comments  two dashes to end of line is a comment, e.g., --this is a comment  Basic Identifiers  Only alphabetic letters ( A-Z, a-z ), or  Decimal digits ( 0-9 ), or  Underline character ( _ )  Must start with alphabetic letter ( MyVal )  Not case sensitive ( LastValue = = lAsTvALue )  May NOT end with underline ( MyVal_ )  May NOT contain sequential underlines (My__Val) Copyright  1997, KJH

34. 06/09/5806/09/5806/09/5806/09/58 34 Lexical Elements of VHDL  Extended Identifiers  Any and all characters enclosed by \ \  Case IS significant  Extended identifiers are distinct from basic identifiers  If “ \ ” is needed in extended identifier, use “ \\ “  Reserved Words  Do not use as identifiers  Special Symbols  Single characters & ‘ ( ) * +, -. / : ; |  Double characters (no intervening space) => ** := /= >= Copyright  1997, KJH

35. 06/09/5806/09/5806/09/5806/09/58 35 Lexical Elements of VHDL  Numbers  Underlines are NOT signifiant ( 10#8_192 )  Exponential notation allowed ( 46e5, 98.6E+12 )  Integer Literals ( 12 )  Only positive numbers, negative numbers preceded by unary negation operator  No radix point  Real Literals ( 23.1 )  Always include decimal point  Radix point must be preceded and followed by at least one digit.  Radix ( radix # number expressed in radix)  Any radix from binary ( 2 ) to hexadecimal ( 16 )  Numbers in radices > 10 use letters a-f for 10-15. Copyright  1997, KJH

36. 06/09/5806/09/5806/09/5806/09/58 36 Lexical Elements of VHDL  Characters  Any printable character including space enclosed in single quotes ( ‘x‘ )  String  A sequence of any printable characters enclosed in double quotes ( “a string” )  Quote using double quote ( “ he said ““no!”” “)  Strings longer than one line use the concatenation operator ( & ) at beginning of continuation line.  Bit Strings  B for binary ( b”0100_1001” )  O for Octal ( o”76443” )  X for hexadecimal ( x”FFFE_F138” ) Copyright  1997, KJH

37. 06/09/5806/09/5806/09/5806/09/58 37 VHDL Syntax  Extended Backus-Naur Form (EBNF)  Language divided into syntactic categories  Each category has a rule describing how to build a rule of that category  Syntactic category <= pattern  “<=“ is read as “...is defined to be...”  e.g., variable_assignment <= target := expression; A clause of the category variable_assignment is defined to be a clause from the category target followed by the symbol “ := “ followed by a clause from the expression category followed by a terminating “ ; ” Copyright  1997, KJH

38. 06/09/5806/09/5806/09/5806/09/58 38 VHDL Syntax Copyright  1997, KJH

39. 06/09/5806/09/5806/09/5806/09/58 39 VHDL Syntax Copyright  1997, KJH