1. Manufacturing Process http://www-micrel.deis.unibo.it/CEDLA

2. General info Date esami:  Giugno  Luglio Sito per le slide o il materiale delle esercitazioni: http://www-micrel.deis.unibo.it/CEDLA Tutor del corso: ing. Elisabetta Farella. Per contattare il tutor: tutorcedla@gmail.com

3. The MOS Transistor

4. Polysilicon Aluminum

5. Cross-Section of CMOS Technology

6. A Modern CMOS Process Dual-well approach

7. Circuit Under Design – Symbolic representation

8. Its Layout View

9. The Manufacturing Process

10. The Silicon Wafer Single-crystal ingot Sliced wafers Important metric: defect density of the base material 10-30 cm diameters, 1mm thickness Doping: 2x10 21 impurities/m 3 Diamond saw Seed crystal Molten Silicon Bath and Czochralski method 2:00 – 4:15

11. Clean Rooms

12. Photolithography 1. Oxidation layering 2. Photoresist coating 3. Stepper exposure 4. Photoresist development and bake 5. Acid Etching 6. Spin, rinse, and dry 7. Various process steps 8. Photoresist removal (or ashing)

13. oxidation optical mask process step photoresist coatingphotoresist removal (ashing) spin, rinse, dry acid etch photoresist stepper exposure development Typical operations in a single photolithographic cycle (from [Fullman]). Photo-Lithographic Process

14. Example: Patterning of SiO2 Si-substrate (a) Silicon base material (b) After oxidation and deposition of negative photoresist (c) Stepper exposure Photoresist SiO 2 UV-light Patterned optical mask Exposed resist SiO 2 Si-substrate SiO 2 2 (d) After development and etching of resist, chemical or plasma etch of SiO 2 (e) After etching (f) Final result after removal of resist Hardened resist Chemical or plasma etch Scaling is getting mask-based steps more and more challenging Done in parallel on the entire wafer

15. Recurring processing step (1) DIFFUSION and ION IMPLANTATION Doping recurs many times. Two approaches:  DIFFUSION IMPLANTATION: wafers in quartz tube in a heated furnace (900-1100 °C); dopants in gas diffuse in the exposed surface vertically and horizontally.  more dopants on the surface than deeper in the material  ION IMPLANTATION (+ annealing): dopants introduced by directing a beam of purified ions over semiconductor surface. Ions accelerations  deepness of penetration; Beam current and exposure time  dosage.  lattice damage. Repair by ANNEALING step (heating based) A wafer handling tray in ion implantation The magnets used to control the ion beam Diffusion furnace

16. Recurring processing step (2) DEPOSITION Repetitively, material is deposited over the wafer (buffering, insulating, etc.). Different techniques depending on materials Chemical vapor deposition (CVD): gas-phase reaction with energy supplied by heat (850°C). Ex. Si 3 N 4 Chemical deposition: Silane gas over heated wafer coated with SiO 2 = Polysilicon non-crystalline amorphous material Sputtering for Alluminium interconnect layers. Alluminium evaporated in vacuum, heated by electron- beam or ion-beam bombarding. … etc.

17. Recurring processing step (3) ETCHING To selectively form patterns (wires, contact holes) Wet etching – use of acid or basic solutions Dry or plasma etching – well defined directionality (sharp vertical contours) PLANARIZATION To ensure a flat surface a chemical-mechanical planarization (CMP) step is included before deposition of extra-metal layer on top of insulating SiO2

18. CMOS Process at a Glance Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers

19. CMOS Process Walk-Through p + p-epi (a) Base material: p+ substrate with p-epi layer p+ (c) After plasma etch of insulating trenches using the inverse of the active area mask p + p-epi SiO 2 3 SiN 4 (b) After deposition of gate-oxide and sacrificial nitride (acts as a buffer layer)

20. CMOS Process Walk-Through SiO 2 (d) After trench filling, CMP planarization, and removal of sacrificial nitride (e) After n-well and V Tp adjust implants n (f) After p-well and V Tn adjust implants p

21. CMOS Process Walk-Through (g) After polysilicon deposition and etch poly(silicon)

22. CMOS Process Walk-Through

23. Advanced Metallization

25. Design Rules

26. 3D Perspective Polysilicon Aluminum

27. Design Rules Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width  scalable design rules: lambda parameter  absolute dimensions (micron rules)

28. CMOS Process Layers Layer Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Well (p,n) Active Area (n+,p+) ColorRepresentation Yellow Green Red Blue Magenta Black Select (p+,n+) Green

29. Layers in 0.25  m CMOS process

30. Intra-Layer Design Rules Metal2 4 3

31. Transistor Layout

32. Vias and Contacts

33. Select Layer

34. CMOS Inverter Layout

35. Layout Editor

36. Design Rule Checker poly_not_fet to all_diff minimum spacing = 0.14 um.

37. Sticks Diagram 1 3 In Out V DD GND Stick diagram of inverter Dimensionless layout entities Only topology is important Final layout generated by “compaction” program

38. Packaging

39. Packaging Requirements Electrical: Low parasitics Mechanical: Reliable and robust Thermal: Efficient heat removal Economical: Cheap Size: small

40. Bonding Techniques

41. Tape-Automated Bonding (TAB)

42. Flip-Chip Bonding

43. Package-to-Board Interconnect (SMD) (c) Ball Grid Array

44. Package Types

45. Package Parameters

46. Multi-Chip Modules