1. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 1 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Bruce Mayer, PE Licensed Electrical & Mechanical Engineer BMayer@ChabotCollege.edu Engineering 43 Boolean Logic Systems

2. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 2 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Analog vs Digital  Up to know we have examined ANALOG systems  In Analog systems the Quantity of Interest (I or V usually) Varies continuously with time → U = f(t)  In the Analog case U plots as a smooth curve vs t  Digital signals are discontinuous in time; ocassionally dU/dt → ∞ (in theory)

3. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 3 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Analog vs Digital Analog Digital Smoothly Varying Curve Vertical Rises & Falls, Flat Tops & Bottoms

4. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 4 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Binary vs MultiLevel Digital U t 1 U t 1 −1  BInary → TWO Level (0/1, Lo/Hi, N/Y) with “Bits” (Binary Digits):  TRInary → THREE Level (−1/0/1, Lo/Med/Hi) with “TRITS”: Zero Levels are Significant

5. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 5 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Binary Logic  Virtually ALL Electronic-Computer Logic is BINARY.  But the Signals are not always “Clean”  A Margin for Error to account for Noisy Signals is called the “Noise Margin”  A Good “NM” allows a weak INput to make a strong Output

6. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 6 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Binary Logic Noise Margains  The NOISE MARGIN is parameter that determines the maximum noise voltage on the input of a gate that allows the output to remain stable.  Two parameters, Low noise margin (NM L ) and High noise margin (NM H ).

7. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 7 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Binary Noise Margins  By the Diagram Above  Inputs in the range V IHmin <V in <V ILmax Produce Unpredictable Results

8. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 8 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Numbering Systems  Numbering Systems (bases) used in Electronic Systems Binary, Base-2 Octal, Base-8 Decimal, Base-10 (Human Base) Hexadecimal, Base-16 (Digit “F 16 ” = 15 10 )  Examples 4623 7 in Decimal  → 1683 10

9. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 9 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Numbering Systems 10^410^310^210^110^0Decimal 10,0001,000100101 426426 16^416^316^216^116^0Decimal 65,5364,096256161 12A298 2^72^62^52^42^32^22^12^0Decimal 1286432168421 1001119 Base 10 Base 16 Base 2

10. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 10 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Counting: Decimal vs Binary  NOTE that 25 10 = 11001 2 DecimalBinaryDecimalBinary 00131101 11141110 210151111 3111610000 41001710001 51011810010 61101910011 71112010100 810002110101 910012210110 1010102310111 1110112411000 1211002511001

11. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 11 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Decimal to Binary Conversion  Method-A  Sucesive Divisions Convert the decimal number 192 into a binary number. 192/2=96with a remainder of0 96/2=48with a remainder of0 48/2=24with a remainder of0 24/2=12with a remainder of0 12/2=6with a remainder of0 6/2=3with a remainder of0 3/2=1with a remainder of1 1/2=0with a remainder of1 Write down all the REMAINDERS, backwards, and you have the binary number 11000000.

12. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 12 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Decimal to Binary Conversion  Method-B  Successive Subtractions Convert the decimal number 192 into a binary number. First find the largest number that is a power of 2 that you can subtract from the original number. Repeat the process until there is nothing left to subtract. 192−128 =64128’s (2 7 ) used1 64 − 64 =064’s (2 6 ) used1 0 − 0 =0 32’s (2 6 ) used0 0 − 0 =0 16’s (2 4 ) used0 0 − 0 =0 8’s (2 3 ) used0 0 − 0 =0 4’s (2 2 ) used0 0 − 0 =0 2’s (2 1 ) used0 0 − 0 =0 1’s (2 0 ) used0 Write down the 0s & 1s from top to bottom, and you have the binary number 11000000.

13. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 13 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Example: Successive Subtracts  Successive subtraction is more intuitive Convert the decimal number 213 into a binary number. First find the largest number that is a power of 2 that you can subtract from the original number. Repeat the process until there is nothing left to subtract. 213-128 = 85128’s (2 7 ) used1 85-64 =21 64’s (2 6 ) used1 *(32 cannot be subtracted from 21) 32’s (2 5 ) used0 21-16 = 5 16’s (2 4 ) used1 *(8 cannot be subtracted from 5) 8’s (2 3 ) used0 5-4=1 4’s (2 2 ) used1 *(2 cannot be subtracted from 1) 2’s (2 1 ) used0 1-1 = 0 1’s (2 0 ) used1 Write down the 0s & 1s from top to bottom, and you have the binary number 11010101.

14. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 14 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Binary to Decimal Conversion  Method-B  Sucessive Additions Make a “Power of 2” table. From right to left, write the values of the power of 2 above each binary number. Then add up the values where a 1 exists. Ex: 10110101 2 2727 2626 2525 2424 23232 2121 2020 1286432168421 10110101 128 + 32 + 16 + 4 + 1 = 181

15. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 15 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Fractional Binary to Decimal  Method-B  Successive Additions Treat Factions the Same way as Integers using successive Additions. Ex: 0.1001101 2 2 −1 2 −2 2 −3 2 −4 2 −5 2 −6 2 −7 2 −8 1/21/41/81/161/321/641/1281/256 10011101 0.5 + 0.0625 + 0.03125 + 0.015625 + 0.0390625 = 0.6133

16. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 16 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Fractional Decimal to Binary  0.417 10 to N 2 by Successive Subtract  Thus after getting to the High-Precision of 7 Sig-Figs Find  Luckily Fractional Conversions are not often need

17. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 17 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Base-16  The Numbers in Base-16 run 0→15 in Decimal  How do we WRITE 13 10 in Base-16 (ONE Symbol) when we’re used to 0→9?  Answer: use LETTERS to represent 10→15

18. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 18 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Hexadecimal to Decimal  Convert 12B 16 to Decimal Base16 Table 16^416^316^216^116^0Decimal 65,5364,096256161 12B299 Each number-place represents a power of 16 Given the hexadecimal number 12B 1 X 256 = 256 2 X 16 = +32 B X 1 = +11 (B = 11 in hex) 299

19. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 19 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis HexaDecimal Numbering  Hexadecimal is the numbering system that is used to represent MAC (Media Access Control) for Internet addresses for example  Another Conversion Example: Express 2F5A 16 as a decimal number 16 3 16 2 16 1 16 0 4096256161 2F5A (2 x 4096) + ([F]15 x 256) + (5 x 16) + ([A]10 x 1) = 12122

20. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 20 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis HexaDecimal Numbering  One hexadecimal character can represent any decimal number between 0 and 15.  In binary, F (15 decimal) is 1111 and A (10 decimal) is 1010.  It follows that 4 bits are required to represent a single hexadecimal value in binary.  A MAC address is 48 bits long (6 bytes), which translates to (48/4 = ) 12 hexadecimal characters required to express a MAC address.  You can check YOUR MAC-ID by typing cmd.exe in Windows-7, and then type in the BlackBox ipconfig/all

21. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 21 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis MAC ID Example  After typing in the Windows “Start Box”: cmd.exe ipconfig/all

22. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 22 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis HexaDecimal Numbering  The smallest decimal value that can be represented by four hexadecimal characters (0000) is 0.  The largest decimal value that can be represented by four hexadecimal characters (FFFF) is 65,535.  It follows that the range of decimal numbers that can be represented by four hexadecimal characters (16 bits) is 0 to 65,535, a total of 65,536 or 2 16 possible values.

23. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 23 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Combinatorial Logic Circuits  The Foundation of Algebra, apart from number themselves, depends on only THREE Operations 1.Negation 2.Addition (OR-ing) 3.Multiplication (AND-ing)  Electronic Circuits can easily implement Inversion OR operations AND operations

24. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 24 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis The Five Base Logic Gates  The Operation of Logic Gates is Described in TRUTH TABLES  Truth Tables Show the OutPut of a Gate as function ONLY of its Inputs  For Example: Inversion or “NOT-ing”  Notice the Logic Gate SYMBOL for an Inverter The Triangle with the Bubble

25. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 25 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis The Five Base Logic Gates  Inverters performs Negation  AND gates perform Multiplication  OR Gates Implement the ADDITION operation

26. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 26 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis The Five Basic Logic Gates  The INVERTED form of an AND is called a Not-AND or NAND. The Truth Table:  The INVERTED form of an OR is called a Not-OR or NOR. The Truth Table:

27. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 27 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis PSPICE Gates  PSPICE-Student has 4 of the 5 Base- Gates as Built-In Parts NAND → 7400 NOR → 7402 INVERT → 7404 AND → 7408

28. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 28 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis The Inversion “Bubble”  The presence of a “Bubble” implies Inversion  For example, a bubble turns a BUFFER into an INVERTER  The Bubble Inverts INPUTS as well as Outputs

29. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 29 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis The EXCLUSIVE GATES  The OR gate produces a “1” for one or two high inputs  The Exclusive-OR allows only one High  The NOR OR gate produces a “0” for one to two low inputs  The Exclusive-NOR allows only one LOW

30. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 30 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis NANDs (or NORs) are Enough  To Build a Functioning logic System Need only: IVERSION, AND, OR (alternatively inversion, nand, nor)  NANDs and NORs are MUCH easier to make than ANDs and NORs.  Thus make Invertors ANDs & ORs from NANDS or NORs NANDS preferred

31. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 31 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis The Logic Gates Summarized

32. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 32 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis WhiteBoard Work  Determine the TRUTH TABLE for  Need 2 4 (16) entries on the Truth Table Next time Write an Equation for the TT

33. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 33 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis All Done for Today Media Access Control A Hexadecimal Number (Note the “E”)

34. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 34 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Bruce Mayer, PE Licensed Electrical & Mechanical Engineer BMayer@ChabotCollege.edu Engineering 43 Appendix NAND

35. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 35 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

36. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 36 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Solution

37. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 37 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Solution by MATLAB % Bruce Mayer, PE % ENGR43 * 25Mar12 % Lec-7a * TruthTable WhiteBoard Problem % file = Truth_Table_Lec7a_1203.m % k = 0; % initialize Vector Counter for A = 0:1; for B = 0:1; for C = 0:1; for D = 0:1; k = k+1; Ai(k) = A; Bi(k) = B; Ci(k) = C; Di(k) = D; Out(k) = ~C&~D | C&D | A&B&D; end % Truth_tbl =[Ai',Bi',Ci',Di',Out']; % disp(' A B C D Out') disp('==================================') disp(Truth_tbl) OutVert = Out'; %debug command A B C D Out ================================ 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 0 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1

38. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 38 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Truth Tables

39. BMayer@ChabotCollege.edu ENGR-43_Lec-06a_Fourier_XferFcn.pptx 39 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis