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Wir schaffen Wissen – heute für morgen 8. Januar 2014PSI,8. Januar 2014PSI, Paul Scherrer Institut Status of CAVITY BPM RFFE & ADC June 24, 2010 Markus.

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Presentation on theme: "Wir schaffen Wissen – heute für morgen 8. Januar 2014PSI,8. Januar 2014PSI, Paul Scherrer Institut Status of CAVITY BPM RFFE & ADC June 24, 2010 Markus."— Presentation transcript:

1 Wir schaffen Wissen – heute für morgen 8. Januar 2014PSI,8. Januar 2014PSI, Paul Scherrer Institut Status of CAVITY BPM RFFE & ADC June 24, 2010 Markus Stadler

2 Talk agenda M. Stadler Cavity BPM RFFE & ADC - Status Seite 2 RFFE overview Mesurement results Redesign measures Performance expectation of BPM system Outlook

3 Front-End redesig: RF section LO generator mixer Range switch 3.3GHz BPF IF amp. / filter M. Stadler Cavity BPM RFFE & ADC - Status Seite 3

4 Prototype RFFE: System overview Seite 4 direct downconversion to (near) zero IF tunable (in steps) LO frequency tunable LO phase on-board conversion clock generation for ADC M. Stadler Cavity BPM RFFE & ADC - Status

5 Pulse response Seite 5 Baseline=ADC-offset M. Stadler Cavity BPM RFFE & ADC - Status

6 Distance measurement principle Seite 6 R Y Basic distance calculation: R and Y are in ADC-LSB, k y is in μm M. Stadler Cavity BPM RFFE & ADC - Status

7 Jitter estimation (1) Seite 7 Estimating position jitter from equivalent ADC input noise Position jitter: k Y : proportionality constant (meas.range/2) Y,R: Y- and Reference channel peak amplitudes (ADC LSB or volts) σ R, σ Y : ADC equivalent input noise (LSB rms or volts rms) Estimation (rather than calculation) because only additive noise is considered ! M. Stadler Cavity BPM RFFE & ADC - Status

8 Jitter estimation Seite 8 RFFE / ADC total noise (ADC equivalent input noise) CHRFFE 1 (μV-rms)RFFE 2 (μV-rms) I_REF Q_REF I_Y Q_Y I_Z Q_Z ADC (LTC2206) high gain mode (FS=1.5Vpp) Measurement: Calculation: System noise (figure) calculation yields 169 μV-rms M. Stadler Cavity BPM RFFE & ADC - Status

9 BPM Prototype Resolution Measurement (SLS-Linac) Seite 9 Measurement principle: Measure of identical signals with two independend BPM Systems and correlate measured distances measured D2 (μm) measured D1 (μm) Assuming identical distributions of measurements D1 and D2: M. Stadler Cavity BPM RFFE & ADC - Status

10 Example measurement series (1) Seite 10 Settings: 0.15nC / 400 μ m ADC: High-Gain mode (FS=1.5Vpp) jitter: 0.61 μm-rms (measured) 0.62 μm (calculated) M. Stadler Cavity BPM RFFE & ADC - Status

11 Example measurement series (2) Seite 11 Settings: 0.3nC / 500μm ADC: High-Gain mode (FS=1.5Vpp) jitter: 0.33 μm-rms (measured) 0.28 μm (calculated) M. Stadler Cavity BPM RFFE & ADC - Status

12 RFFE Pulse Linearity Measurements Seite 12 ADC FS Prototype System pulse linearity: M. Stadler Cavity BPM RFFE & ADC - Status

13 Front-End redesig: Local temperature control Prototype RFFE temperature dependence suggests that temperature should be stabilized to better than 0.5 ºC In redesigned RFFE several local temperature control loops applied Measured amplitude temperature dependence of prototype RFFE Temperature: Absolute amplitude drift (incl. switch-on drift): Drift of amplitude ratio: Ca. 0.1% per deg-C M. Stadler Cavity BPM RFFE & ADC - Status Seite 13

14 Conclusion from Measurements Seite 14 Measurement jitter is < 1 μm Measured jitter in good agreement with calculation Temperature sensitivity needs improvement Linearity is within 2% Additive noise sources in signal chain dominate the jitter performance Synthesizer phase noise / timing jitter do not significantly degrade performance Redefinition of charge ranges improves resolution local temperature control Measurements on prototype system suggest the following conclusions: not much margin ! Difficult to measure simple and cheap PLL- synthesizers can be retained M. Stadler Cavity BPM RFFE & ADC - Status

15 Front-End Redesign (1) Seite 15 RFFE control via single I 2 C-bus Temperature controlled critical circuit parts 216 MHz machine reference (previously 81MHz) IF-amplifier redesigned providing gain control (Pick-up tolerances) Redefinition of charge ranges Hot-Swap controlling Main RFFE design changes: M. Stadler Cavity BPM RFFE & ADC - Status

16 Front-End redesign (2) RF Phase Control (360 deg) RF frequency control (9MHz steps) Conversion Clock Phase Control 12 Local Temperature Stabilizaiton areas on the PCB (analog or digital) around sensitive circuit parts Charge Range control (3 ranges from 0.1 to 1nC, 1 low charge range) 160MHz / +12dBm ADC clock output Main RFFE design changes: M. Stadler Cavity BPM RFFE & ADC - Status Seite 16

17 Front-End redesig: Local temperature control Local temperature control circuit: Temperature sensitive circuits are locally heathed at 2-5ºC above their free-running steady state temperature. This will consume about 300mA of extra current (whole RFFE) Temperature stabilization: analog or digital control Temperature readout resolution 0.04 ºC M. Stadler Cavity BPM RFFE & ADC - Status Seite 17

18 Front-End redesig: RF section Prototype: 2 charge ranges Upper range: 0.3-1nC Lower range: nC Charge ratio =3.3 Redesigned: 3+1 charge ranges Upper range: nC Mid range: nC Low range: nC (additional range: <0.1 nC) charge ratio =2.1 Max position jitter ~ (charge ratio) · (meas. range) M. Stadler Cavity BPM RFFE & ADC - Status Seite 18

19 Linearity dictates 0dBm at full-scale offset and charge Minimum pickup sensitivity: 0dBm at mixer max. beam offset and upper bound of lowest charge range (WITHOUT an RF amplifier) In our case (2.2dB cable loss for 6m of RF cable and 0.21nC bunch charge): 6 mV/(nC·um) for ±1000 um 3 mV/(nC·um) for ±500 um Cable lossRF-path loss Pick-Up sensitivity for lower charge ranges First priorities to maintain resolution at lower charge ranges (<0.1nC) would be: Reduce losses in cable and RFFE RF-part Increase pick-up sensitivity M. Stadler Cavity BPM RFFE & ADC - Status Seite 19

20 Redesigned RFFE block diagram M. Stadler Cavity BPM RFFE & ADC - Status Seite 20

21 Expected Performance of 2 nd Prototype Seite 21 Single bunch resolution (μm-rms) Performance estimation based on calculations and measurements on 1 st prototype: Temperature sensitivity <0.3 %/ºC linearity<2% Bunch to bunch crosstalk <1 μm (digital comp.) For a complete list of performance numbers see project doc. Charge Range Charge (nC) Beam offset (μm) high mid low M. Stadler Cavity BPM RFFE & ADC - Status

22 Outlook Seite 22 StatusStart dateEnd date Schematic drawing Review PCB layout StartedJul 2010 Mechanical drawings (shield, front-panel Aug 2010 PCB assembly Aug 2010 Laboratory tests Sept 2010 Tests (SwisFEL 250MeV injector) Sept 2010 (?) Tests FLASH Nov 2010 (?) M. Stadler Cavity BPM RFFE & ADC - Status

23 Seite 23 Thanks ! M. Stadler Cavity BPM RFFE & ADC - Status


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