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MT rf 800 kW connection to PETRA-III controlsystem The ELWIS-concept of MHF-e for PETRA-III 2 klystrons transmitter high voltage power supply 6 cavities.

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Presentation on theme: "MT rf 800 kW connection to PETRA-III controlsystem The ELWIS-concept of MHF-e for PETRA-III 2 klystrons transmitter high voltage power supply 6 cavities."— Presentation transcript:

1 MT rf 800 kW connection to PETRA-III controlsystem The ELWIS-concept of MHF-e for PETRA-III 2 klystrons transmitter high voltage power supply 6 cavities additional modulator power supply rf-regulation distribution vacuum 75kV/36A Stefan Wilke, MHF-e, to 2. transmitter

2 DAC 16bit 16 x communication local intelligence ELWIS brain fast ADC 14 bit 10MHz ±1V 4 x ext. clk ext. trigger int. trigger out I/Q demod. Software generated trigger hard disk Compact Flash fast ADC 14 bit 10MHz ±1V 4 x ext. clk ext. trigger int. trigger out I/Q demod. Software generated trigger ADC 16 bit 200kHz ±10V 16 x Dig. In/Out 192 x ELWIS : egg laying wool milk sow 2 FPGA NI 7831R PXI Stefan Wilke, MHF-e, kit: PXI crate (19), controller (PC), FPGA (digital and analog in-/outputs), fastADC (10MHz) incl. transientrecorder (800ms), trigger- and sync.-distribution, signal preparation (Phoenix), uninterrupted power supply

3 Stefan Wilke, MHF-e, FPGA 1. FPGA trigger and sync

4 implementation I 28 ELWIS-moduls (PXI crates, 19 inch) Microsoft Windows XP LabVIEW (LV) 8.0 from National Instruments (NI) programming of NI-FPGA-cards in LabVIEW (no VHDL-knowledge necessary!) communication in TINE (ethernet) each ELWIS module differ only in software (modularity, CF) radiationtest in DORIS (one FPGA fault at 45 Gy) control of steppermotors (tuner in cavity) implemented in FPGA code written by us the 8 channels of fast ADC (10MHz I/Q) includes transientrecorders (800ms) Stefan Wilke, MHF-e,

5 implementation II Anzahl pro Sender ELWISCavityModulatorKlystronSenderSonst.VerteilungHF-RegelungSumme Fast Analog Eingänge : Analog Eingänge : DAC Out Digital Eingänge : Digital Ausgänge : pro ELWIS pro Typ bei 1 Sender Gesamtanlage930 ca FPGA LV is a simple grafic software running in data flow model, at DESY in many groups often used. Without spezial knowledge we reach in teams of many colleagues (no computer scientist, but technician and engineers) pragmatic results. Very good TINE support at DESY. Many TINE-VIs ready for LabVIEW. number of signals: security: paranoid – naive. isolated net. authorization of active switching will manageTINE stability: example: since in DORIS-tunnel

6 Stefan Wilke, MHF-e, example of a LabVIEW-program

7 Stefan Wilke, MHF-e, example of writing FPGA-code in LabVIEW thank you!

8 fast ADC card Stefan Wilke, MHF-e,

9 test of a cavity-ELWIS Stefan Wilke, MHF-e,


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