1. ISAT 436 Micro-/Nanofabrication and Applications MOS Transistor Fabrication David J. Lawrence Spring 2001

2. VLSI and ULSI Integrated Circuits H The same integrated circuit die is usually replicated hundreds of times on a typical silicon wafer. H More complex circuits require more transistors and consequently a larger chip area.  Figure 1.1 on page 3 of Jaeger gives the approximate number of 5 mm  5 mm dice that can be fabricated simultaneously on a wafer as a function of the wafer diameter.

3. Transistors H Recall that there are two major types of transistors: G Bipolar Junction Transistors (BJTs) G Field Effect Transistors (FETs) H Both of these categories can be further broken down into sub-categories: G BJTs -- npn, pnp, heterojunction G FETs -- MESFETs, MOSFETs H There are several types of MOSFETs: G n-channel (NMOS), p-channel (PMOS) G enhancement mode, depletion mode

4. Transistors H Bipolar Junction Transistors (BJTs) have the following features: G high gain (current amplification) G fast switching/high frequency amplification H Field Effect Transistors (FETs) have the following features: G smaller than BJTs G consume less power than BJTs G fewer mask levels required than for BJTs

5. NMOS and NPN Transistors H The cross section and composite top view of an n-channel metal-oxide-semiconductor (NMOS) transistor are shown in Figure 1.2 on page 4 of Jaeger. H The cross section and composite top view of an npn bipolar junction transistor are shown in Figure 1.3 on page 5 of Jaeger.

6. NMOS Fabrication Process (1) H The process sequence for an NMOS transistor fabrication process is illustrated in Figure 1.4 on page 7 of Jaeger. H A flowchart for the NMOS fabrication process is shown in Figure 1.5 on page 8 of Jaeger. H The starting material is a p-type silicon wafer. H We shall go through this process step by step. H The letter “bullets” (a, b, c, …) refer to the corresponding diagrams in Figure 1.4 on page 7 of Jaeger.

7. NMOS Fabrication Process (2) (a)Grow “thin-pad” layer of SiO 2 and deposit Si 3 N 4 layer by CVD. (b)(1) Mask #1 -- Photolithography and etching to define the active NMOS transistor areas. Remove SiO 2 and Si 3 N 4 everywhere else by etching. (2) Then do boron ion implantation (“field implant”). This improves isolation of neighboring transistors from one another.

8. NMOS Fabrication Process (3) (c) (1) Grow thick oxide (“field oxide”) outside the transistor areas. (2) Remove Si 3 N 4 and thin pad SiO 2 by etching. (3) Grow thin “gate oxide” (the oxide that will separate the polysilicon gate from the transistor channel. (4) Ion implant boron to adjust the transistor threshold voltage to the desired value (gate voltage needed to turn on the transistor). (5) Deposit polysilicon (CVD) over entire wafer.

9. NMOS Fabrication Process (4) (d)(1) Mask #2 -- Photolithography and etching to define the polysilicon gate regions and interconnections. Remove poly everywhere else by etching. (2) Ion implant arsenic or phosphorus to dope the source and drain regions and the polysilicon gate material (n-type). (3) The implanted dopant is “activated” and usually driven deeper into the wafer with a high temperature diffusion step.

10. NMOS Fabrication Process (5) (e)(1) Deposit protective oxide ( SiO 2 ) by CVD. (2) Mask #3 -- Photolithography and etching to open contact windows. (f)(1) Deposit metal (aluminum) over entire wafer surface by sputtering or evaporation. (2) Mask #4 -- Photolithography and etching to pattern the aluminum metal layer to produce the desired metal interconnection pattern. Etch away the aluminum where it is not wanted.

11. NMOS Fabrication Process (6) (g)Not Shown (1) Deposit a passivation (protective) layer of phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG) over the entire wafer surface. (2) Mask #5 -- Photolithography and etching to open windows in the PSG or BPSG passivation layer so bonding wires can be attached to the aluminum “bonding pads” on the periphery of each IC die.

12. NMOS Fabrication Process (7) (h)Not Shown (1) Individual IC dice are separated from one another by sawing or by scribing and breaking the wafer (Jaeger p. 154). (2) Each IC die is attached to a package or “header” with an epoxy adhesive or a metal alloy solder (Jaeger pp. 154-155). (3) Wire bonding is the most common method for making electrical connections between the aluminum bonding pads on the periphery of each IC die and the package (Jaeger pp. 155- 159, and Figure 8.4).

13. NMOS Fabrication Process (8) H There are several important features of this NMOS fabrication process: G There are 5 mask steps. G Each of these mask steps uses a “subtractive” (etching) process. G I.e., the entire surface of a wafer is first coated with the desired material. G Then, the material is removed from areas where it is not wanted by wet chemical etching or plasma (dry) etching. G Additional insulating layers, metal layers, and mask steps can be added to enable more complex interconnection of transistors.

14. CMOS Process H Most logic circuits are constructed from complementary MOS (CMOS) devices. Why? H This requires NMOS and PMOS transistors to be fabricated on the same wafer. H See pages 8 and 9 of Jaeger. H This requires more mask levels. H Still more mask levels are used for complex interconnections.

15. Bipolar Process H The basic bipolar process is more complex than the NMOS process (Jaeger pp. 10-11). H Seven mask levels vs. five for NMOS. H Epitaxial growth is usually used. H Review the comparison of field effect transistors (FETs) and bipolar junction transistors (BJTs) in an early slide.