1. Renesas Electronics America Inc. © 2012 Renesas Electronics America Inc. All rights reserved. Class ID: Migrating from 8-to-32 bit Processors CC17I Kevin P King - Senior Staff Application Engineer

2. © 2012 Renesas Electronics America Inc. All rights reserved.2 Kevin P King Education Electrical Engineering, University of Lowell (Edward B Van Dusen Award for Academic Achievement) Thirty years of Embedded Design Experience (x86, HC05, HC11, 8051, Philips XA, Atmel AVR, Hitachi, Mitsubishi, etc.... Five years of Emulator design for MetaLink COP8, 68HC05, 68HC11, 8051 (multi-vendors), National CR16, Hitachi H8/500, etc... Multiple quality qwards for embedded software & hardware development. Specialty is embedded system design - MCU firmware & hardware Senior Staff Application Engineer RX DSP Library development team Numerous motor control and medical App notes 2010 Patent Award for motor control

3. © 2012 Renesas Electronics America Inc. All rights reserved.3 Renesas Technology & Solution Portfolio

4. © 2012 Renesas Electronics America Inc. All rights reserved.4 Microcontroller and Microprocessor Line-up Wide Format LCDs  Industrial & Automotive, 130nm  350µA/MHz, 1µA standby 44 DMIPS, True Low Power Embedded Security, ASSP 165 DMIPS, FPU, DSC 1200 DMIPS, Performance 1200 DMIPS, Superscalar 500 DMIPS, Low Power 165 DMIPS, FPU, DSC 25 DMIPS, Low Power 10 DMIPS, Capacitive Touch  Industrial & Automotive, 150nm  190µA/MHz, 0.3µA standby  Industrial, 90nm  200µA/MHz, 1.6µA deep standby  Automotive & Industrial, 90nm  600µA/MHz, 1.5µA standby  Automotive & Industrial, 65nm  600µA/MHz, 1.5µA standby  Automotive, 40nm  500µA/MHz, 35µA deep standby  Industrial, 40nm  200µA/MHz, 0.3µA deep standby  Industrial, 90nm  1mA/MHz, 100µA standby  Industrial & Automotive, 130nm  144µA/MHz, 0.2µA standby 2010 2012 32-bit 8/16-bit

5. © 2012 Renesas Electronics America Inc. All rights reserved.5 Challenge: “Many ‘Smart’ applications require the performance of a 16 or 32 bit processor to do their job.” ‘Enabling The Smart Society’ Solution: “This class will help you avoid some of the more annoying problems you may encounter as you move your design from 8 to 32 bit and into the Smart Society”

6. © 2012 Renesas Electronics America Inc. All rights reserved.6 Agenda Genesis of problem Why do I care? Core size Accessing SFRs Variable alignment Structure alignment Working code versus portable code Summary Q&A

7. © 2012 Renesas Electronics America Inc. All rights reserved.7 Creating a Problem Microprocessor native size Intel versus Motorola

8. © 2012 Renesas Electronics America Inc. All rights reserved.8 Do I need to do anything different? Processor core size Endianness Coding style Portability

9. © 2012 Renesas Electronics America Inc. All rights reserved.9 Why do I care? Porting code (requirement 1) Legacy code / existing IP Code compatibility (requirement 2) Back to existing designs Shared memory / communication with other MCU Playing nicely with others (requirement 3) Memory mapped IO Existing FPGA and ASIC designs (requirement 4) The perfect device, but wrong endianness

10. © 2012 Renesas Electronics America Inc. All rights reserved.10 Hardware Register Access Issue Word decode only Register coherency Rule Access all hardware the way the manual or the hardware designer tells you to.

11. © 2012 Renesas Electronics America Inc. All rights reserved.11 Hardware Register Access Issue union my_reg { unsigned short WORD; struct { unsigned short rsrvd2:8; unsigned short rsrvd1:6; unsigned short MY_BIT2:1; unsigned short MY_BIT1:1; } BIT; } __evenaccess MY_REG; RX solution / example Access size is guaranteed for 4-byte or smaller scalar integer types (signed char, unsigned char, signed short, unsigned short, signed int, unsigned int, signed long, and unsigned long).

12. © 2012 Renesas Electronics America Inc. All rights reserved.12 Hardware Register Access Issue Code without regard to access size MY_REG.BIT.MY_BIT2 &= 0; address of MY_REG -> R5 Clear Bit #6 @[R5]+1 MY_REG.BIT.MY_BIT2 &= 0; Address of MY_REG -> R4 @[R4] -> R5 Clear Bit #14 of R5 R5 -> @[R4] Code with “forced” access size

13. © 2012 Renesas Electronics America Inc. All rights reserved.13 If you don’t have “evenaccess” feature in your compiler, how would you limit the type of access to a hardware register? Question? Possible solutions Declare port as the correct width and enumerate the bits Public function for setting and clearing bits If in doubt - Review the code generated by compiler

14. © 2012 Renesas Electronics America Inc. All rights reserved.14 Type Sizes union date_union { unsigned long year_month_day; struct{ unsigned int year; unsigned char month; unsigned char day; }word_and_byte; } date = { 0x20121022}; Legacy Code (requirement 1) read_monthH'00 '.' read_dayH'00 '.' read_yearH'20121022

15. © 2012 Renesas Electronics America Inc. All rights reserved.15 Endianness union date_union { uint32_t year_month_day; struct{ uint16_t year; uint8_t month; uint8_t day; }word_and_byte; } date = { 0x20121022};

16. © 2012 Renesas Electronics America Inc. All rights reserved.16 Endianness Definition Wiki- “refers to the ordering of individually addressable sub- components within the representation of a larger data item as stored in external memory (or, sometimes, as sent on a serial connection).”external memory Big-Endian Most Significant appears first (lowest address) in memory Little-Endian Least Significant appears first (lowest address) in memory

17. © 2012 Renesas Electronics America Inc. All rights reserved.17 Endianness union date_union { uint32_t year_month_day; struct{ uint16_t year; uint8_t month; uint8_t day; }word_and_byte; } date = { 0x20121022};

18. © 2012 Renesas Electronics America Inc. All rights reserved.18 Endianness union date_union { uint32_t year_month_day; struct{ uint16_t year; uint8_t month; uint8_t day; }word_and_byte; } date = { 0x20121022}; Unions – be aware of byte ordering read_monthH'12 '.'{ 00001401 }(unsigned char)[Current Scope] read_dayH'20 ' '{ 00001400 }(unsigned char)[Current Scope] read_yearH'1022{ 0000147E }(unsigned short)[Current Scope]

19. © 2012 Renesas Electronics America Inc. All rights reserved.19 Endianness

20. © 2012 Renesas Electronics America Inc. All rights reserved.20 Endianness (cont’d) typedef union char_union{ uint8_t char_data; struct{ uint8_t c_data:7; uint8_t parity:1; }BIT; } comm_char; Communications (requirement 3) uint8_t strip_parity(comm_char * com_char_to_proc) { return(com_char_to_proc->BIT.c_data); // remove parity bit }

21. © 2012 Renesas Electronics America Inc. All rights reserved.21 Endianness 0x550x6a Bit alignment usually goes along with endianness Solutions Compiler switch (available in RX) to change bit-packing Conditional coding of the structure return(com_char_to_proc->BIT.c_data); // remove parity bit

22. © 2012 Renesas Electronics America Inc. All rights reserved.22 Endianness Communications (requirement 3) #define LITTLE_ENDIAN typedef union char_union{ uint8_t char_data; struct{ #ifdef LITTLE_ENDIAN uint8_t c_data:7; uint8_t parity:1; #else uint8_t parity:1; uint8_t c_data:7; #endif }BIT; } comm_char;

23. © 2012 Renesas Electronics America Inc. All rights reserved.23 Endianness Casting and pointer de-referencing (requirement 3) uint16_t short_data = {0x1234}; uint8_t *p_char; uint16_t s_data; uint8_t c_data; s_data = short_data; p_char = (unsigned char *)&short_data; c_data = *p_char; Watch Window c_data = 0x12

24. © 2012 Renesas Electronics America Inc. All rights reserved.24 External Bus Operation (requirement 4) Endianness support MSBLSB MSB Little-Endian Processor General Purpose register Big-Endian ASIC General Purpose Registers 0 1 Register Address Little-Endian MCU to Little-Endian Bus Access

25. © 2012 Renesas Electronics America Inc. All rights reserved.25 External Bus Operation (requirement 4) Endianness support in Bus State Controller (BSC) MSBLSB MSB Little-endian Processor General Purpose register Big-Endian ASIC General Purpose register 0 1 Register Address Little-Endian MCU to Big-Endian bus access

26. © 2012 Renesas Electronics America Inc. All rights reserved.26 Variable Alignment Issues Packing #pragma pack union date_union{ uint32_t year_month_day; struct{ uint8_t day; uint16_t year; uint8_t month; }word_and_byte; } date; #pragma unpack #pragma pack union date_union{ uint32_t year_month_day; struct{ uint8_t day; uint16_t year; uint8_t month; }word_and_byte; } date; #pragma unpack

27. © 2012 Renesas Electronics America Inc. All rights reserved.27 Variable Alignment Issues - Packing Packing may result in unaligned word / long access Possible address exception Additional bus cycles

28. © 2012 Renesas Electronics America Inc. All rights reserved.28 Variable Alignment Issues Compiler Alignment Usually aligns on a boundary based on the elements size Can be controlled by sections Can lead to wasted space in some tool chains General rule of thumb If unsure of the compiler and linker operations, where possible declare your variables from Largest to smallest. uint8_t day; uint16_t year; uint8_t month;

29. © 2012 Renesas Electronics America Inc. All rights reserved.29 Sections ANSI does NOT define sections Common section naming (implementation specific) P – Program section(code) C – Const section D – Initialized variables section (ROM Image) R – Initialized variable RAM section(D usually gets copied here) B – Un-initialized variables (RAM) RX enhancement (one example) B_1 – Byte aligned variable section B_2 – Word aligned variable section B – Long aligned variable section

30. © 2012 Renesas Electronics America Inc. All rights reserved.30 Unaligned Word Accesses (HW) RL78 Compile time OK Runtime gives invalid results R8C - OK, 8-bit bus always two cycles RX – OK, but added bus cycles SH2A Compile time OK Runtime gives Address exception

31. © 2012 Renesas Electronics America Inc. All rights reserved.31 Memory Access RX unaligned word my_year = year; Read LS Byte on First Cycle at address n Read MS Byte on Second Cycle at address n + 2

32. © 2012 Renesas Electronics America Inc. All rights reserved.32 Memory Access RX unaligned word

33. © 2012 Renesas Electronics America Inc. All rights reserved.33 Memory Access RX unaligned word (external 16 Bus) RX Asserts #RD, A1=0 Entire word appears on bus RX “holds” upper byte RX Asserts #RD, A1=1 Entire word appears on bus RX merges MSByte with “held” LSByte

34. © 2012 Renesas Electronics America Inc. All rights reserved.34 The Final Solution on structures and unions Fixes alignment, size, no wasted space, initialization union date_union{ uint32_t year_month_day; struct{ uint16_t year; uint8_t month; uint8_t day; }word_and_byte; } date; void init_date(uint16_t year, uint8_t month, uint8_t day) { date.word_and_byte.month = month; // initialize by struct name date.word_and_byte.day = day; // avoid any alignment date.word_and_byte.year = year; // issues } Stdint type to avoid size issues Public function to initialize by name to avoid Endian issues caused by initializing the long statically Declared largest to smallest so alignment will not likely be an issue and Bytes will likely be packed right up against the word

35. © 2012 Renesas Electronics America Inc. All rights reserved.35 Math Operations Hardware support MUL/DIV/MAC Barrel-Shift FPU Issues with type sizes int my_multiplier; int my_int; my_int *= my_multiplier; /* calculate the new result */ if (my_int & 0x8000) /* check for overflow */ { overflow_error(); /* flag the error */ } int16_t my_multiplier; int16_t my_int; my_int *= my_multiplier; /* calculate the new result */ if (my_int & 0x8000) /* check for overflow */ { overflow_error(); /* flag the error */ }

36. © 2012 Renesas Electronics America Inc. All rights reserved.36 Atomic Operations “An atomic operation is an operation that will always be executed without any other process being able to read or change state that is read or changed during the operation.” Definition from OS Dev.org Stated in simple terms - an operation that cannot be interrupted

37. © 2012 Renesas Electronics America Inc. All rights reserved.37 Atomic Operations Simple 32 bit counter in RAM on 16 bit processor Interrupt based timer ticks it Other tasks only read it 0x00000xFFFF SW_Cntr Local_Cntr=SW_Cntr; Function_A Task A reads MS Word for Local_Cntr=0x0000 Timer_ISR SW_Cntr++; 0x00010x0000SW_Cntr (resumes) Task A reads LS Word for Local_Cntr=0x0000 Local_Cntr = 0x00000000 !!!!!! Function_A

38. © 2012 Renesas Electronics America Inc. All rights reserved.38 Atomic Operations #define BUFF_SIZE 128 // should not exceed 256 typedef struct { uint8_t data_in_indx; uint8_t data_out_indx; uint8_t sts_flag; uint8_t data[BUFF_SIZE]; } CIRCULAR_BUFF; Classic atomic operation (pseudo code)  Disable Interrupts;  Operate on element(s);  Enable interrupts; For RX, you can use XCHG xchg(&is_locked, &plock->lock)

39. © 2012 Renesas Electronics America Inc. All rights reserved.39 Guidelines Use coding standards in your company Use Static analysis tools Reduce the affects of variable size (C99 stdint.h) Account for the endianness of your processor Use any HW support available Code for portability Understand portability requirements Understand your processor’s access size limitations Take a “macro” rather than a “micro” perspective

40. © 2012 Renesas Electronics America Inc. All rights reserved.40 Summary Genesis of problem Why do I care? Core size Accessing SFRs and other hardware Variable alignment Structure / Union element alignment Working code versus portable code

41. © 2012 Renesas Electronics America Inc. All rights reserved.41 Questions? Questions?

42. © 2012 Renesas Electronics America Inc. All rights reserved.42 Challenge: “Many “Smart Applications” applications require the performance of a 16 or 32 bit processor to do their job.” “This class will help you avoid some of the more annoying problems you may encounter as you move your design from 8 to 32 bit and into the Smart Society” Do you agree that we accomplished the above statement? ‘Enabling The Smart Society’ in Review…

43. © 2012 Renesas Electronics America Inc. All rights reserved.43 Please utilize the ‘Guidebook’ application to leave feedback or Ask me for the paper feedback form for you to use… Please Provide Your Feedback…

44. © 2012 Renesas Electronics America Inc. All rights reserved.44 Thank You!

45. © 2012 Renesas Electronics America Inc. All rights reserved.45 Appendix: Additional Information

46. © 2012 Renesas Electronics America Inc. All rights reserved.46 Resources & References http://en.wikipedia.org/wiki/Lilliput_and_Blefuscu http://en.wikipedia.org/wiki/Endianness Embedded C Coding Standard, Netrino The C Programming Language, Kernighan & Ritchie International Standard ISO/IEC 9899:1999(E) MISRA-C:2004, Guidelines for the use of C language in Critical Systems. http://www.misra.org.uk/http://www.misra.org.uk/ PCLint for C/C++, http://www.gimpel.com/html/index.htmhttp://www.gimpel.com/html/index.htm Renesas Application note, R01AN0186EJ0100, Software Code and Endian Effects

47. Renesas Electronics America Inc. © 2012 Renesas Electronics America Inc. All rights reserved.

48. 48 Word Decode Access Issue MOV.L #CS_REG,R5 MOV.B R3,01H[R5] Circuit ACircuit B