1. NIKHEF 27 Feb 2007RELAXd Serial Readout Status1 RELAXd Serial Readout - Status Motherboard MASTER RELAXd Chipboard – SLAVE ADCDACsFlashPower FPGA LatticeSC15 MPix0 Serial data up to 600Mbps control MPix1 MPix2 MPix3 up to 3Gbps Ext. inputs (ext. shutter etc.) SLAVE 2 SLAVE 3 etc. serial 8b/10b Idea:

2. NIKHEF 27 Feb 2007RELAXd Serial Readout Status2 Master – Slave Communication Protocol 16bit words SOP Header Index++, length Command ID Command Parameters/Data CRC EOP Trailer 16bit words SOP Index++, length Data CRC EOP Header Trailer Only one command (Mpix_Mode, Read_Status, Set_Config, Set_Int_DAQ) in each command block (no command list necessary) Commands/data sent from Master to Slave Data sent from Slave/MPix to Master

3. NIKHEF 27 Feb 2007RELAXd Serial Readout Status3 Implementation - Schematics of Data Path PCS 8b/10b FIFO_Out 16b x 512 OSCA 130MHz Pcs_Out SM 16b 1b 3GHz 150 MHz 16b FIFO_In 16b x 512 Pcs_In SM 16b SM reset SDR_Out_0 600 MHz SDR_Out_1 SDR_Out_2 SDR_Out_3 4b 1b to MPix Quad to Master SDR_In_0 SDR SM 16b SDR_In_1 SDR_In_2 SDR_In_3 4b 1b 16b fClock_in Int. DAQ Control SM FPGA Data_Out Data_In M0, M1,Shutter, Enable_In, Reset Enable_out Ext_shutter Ext_clk delay0 delay1 delay2 delay3 PLL DLL reset type TX_STATE_TYPE is (IDLE, SENDING_DATA); type RX_STATE_TYPE is (ERROR, IDLE, READING_DATA, M_RESET); type MPIX_STATE_TYPE is (ERROR, IDLE, READ_COMMAND, SET_MPIX_MODE, SETTING_MATRIX, READING_MATRIX, SETTING_DACS, COUNTING, RESETTING_MATRIX);

4. NIKHEF 27 Feb 2007RELAXd Serial Readout Status4 SDR Block – gearing 4 to 1 Channel data_out to fast_clock alignment

5. NIKHEF 27 Feb 2007RELAXd Serial Readout Status5 Clock Path (backup) PCS 8b/10b FIFO_Out 16b x 512 OSCA 130MHz Pcs_Out SM 3GHz 150 MHz FIFO_In 16b x 512 Pcs_In SM SDR_Out_0 600 MHz SDR_Out_1 SDR_Out_2 SDR_Out_3 1b to MPix Quad to Master SDR_In_0 SDR SM SDR_In_1 SDR_In_2 SDR_In_3 1b fClock_in FPGA Data_Out Data_In M0, M1,Shutter, Enable_In, Reset Enable_out Ext_shutter Ext_clk delay0 delay1 delay2 delay3 PLL DLL reset fClk DIV/4 sClk rx_clk rx_refClk tx_refClk

6. NIKHEF 27 Feb 2007RELAXd Serial Readout Status6 Clock Path (baseline) PCS 8b/10b FIFO_Out 16b x 512 OSCA 130MHz Pcs_Out SM 3GHz 150 MHz FIFO_In 16b x 512 Pcs_In SM SDR_Out_0 600 MHz SDR_Out_1 SDR_Out_2 SDR_Out_3 1b to MPix Quad to Master SDR_In_0 SDR SM SDR_In_1 SDR_In_2 SDR_In_3 1b fClock_in FPGA Data_Out Data_In M0, M1,Shutter, Enable_In, Reset Enable_out Ext_shutter Ext_clk delay0 delay1 delay2 delay3 PLL_ref DLL reset fClk DIV/4 sClk rx_clk rx_refClk tx_refClk PLL

7. NIKHEF 27 Feb 2007RELAXd Serial Readout Status7 entity top is port ( -- CMOS global_reset: in std_logic; -- reset button ? ext_clk: in std_logic; -- clock from ext. oscilator ext_shutter: in std_logic; -- LVDS medipix mpix0_data_in: out std_logic; mpix1_data_in: out std_logic; mpix2_data_in: out std_logic; mpix3_data_in: out std_logic; mpix0_fclock_in: out std_logic; mpix1_fclock_in: out std_logic; mpix2_fclock_in: out std_logic; mpix3_fclock_in: out std_logic; mpix0_enable_in: out std_logic; mpix1_enable_in: out std_logic; mpix2_enable_in: out std_logic; mpix3_enable_in: out std_logic; mpix0_data_out: in std_logic; mpix1_data_out: in std_logic; mpix2_data_out: in std_logic; mpix3_data_out: in std_logic; mpix0_enable_out: in std_logic; mpix1_enable_out: in std_logic; mpix2_enable_out: in std_logic; mpix3_enable_out: in std_logic; -- CMOS medipix mpix_reset: out std_logic; -- active low! mpix0_shutter: out std_logic; -- or common to all? mpix1_shutter: out std_logic; mpix2_shutter: out std_logic; mpix3_shutter: out std_logic; mpix_M: out std_logic_vector(1 downto 0); --- mpix0_spareFSR: out std_logic; -- only in mpix2.1 --- mpix1_spareFSR: out std_logic; --- mpix2_spareFSR: out std_logic; --- mpix3_spareFSR: out std_logic; mpix_polarity: out std_logic; mpix_p_s: out std_logic; --set to 0 !! mpix_enable_tpulse: out std_logic; -- pcs serial inputs/outputs pcs_hdinp_0, pcs_hdinn_0 : in std_logic; pcs_hdoutp_0, pcs_hdoutn_0 : out std_logic ); end; ADC/DAC/Power IO not included yet! Total: LVDS I/O - 8/12 + serdes 1/1 CMOS I/O - > 3/10 FPGA Inputs/Outputs

8. NIKHEF 27 Feb 2007RELAXd Serial Readout Status8 FPGA Inputs/Outputs notes: Serdes CH0, for debugging maybe also useful another channel (CH1) external shutter Ref clock (CMOS ?) Reset and Load_Config buttons would be nice to have some probe pins (2 to 4 ?) additional switches (2 ?) and status LEDs (4 ?) DAC/ADS/Power chip IO’s … something else ???

9. NIKHEF 27 Feb 2007RELAXd Serial Readout Status9 SC15 IO Data Sheet Fpga LatticeSC15 – 139 IO pins, 4 SERDES, 17x17mm (256-ball fpBGA pack).

10. NIKHEF 27 Feb 2007RELAXd Serial Readout Status10 1 2 3 45 7 6

11. NIKHEF 27 Feb 2007RELAXd Serial Readout Status11 FPGA SC15 Utilization

12. NIKHEF 27 Feb 2007RELAXd Serial Readout Status12

13. NIKHEF 27 Feb 2007RELAXd Serial Readout Status13

14. NIKHEF 27 Feb 2007RELAXd Serial Readout Status14

15. NIKHEF 27 Feb 2007RELAXd Serial Readout Status15 FPGA SC15 Power Calculation

16. NIKHEF 27 Feb 2007RELAXd Serial Readout Status16 Test Bench Setup – SC25 Evaluation Board PCS 8b/10b FIFO_Out 16b x 512 Pcs_Out SM 16b1b 3GHz 150 MHz 16b FIFO_In 16b x 512 Pcs_In SM 16b Reset_bypass SDR_Out_0 SDR_Out SM 16b 600 MHz SDR_Out_1 SDR_Out_2 SDR_Out_3 4b 1b to MPix to Master SDR_In_0 SDR_In SM 16b SDR_In_1 SDR_In_2 SDR_In_3 4b 1b Command Status Registers 16b x 16 Command SM 16b fClock MPix Control SM FPGA Jtag_Tracy “Logic Analyzer” OSCA Clk_130MHz “Master” Control Emulator 1b PCS m Jtag-USB PCS ethernet Marvell Ethernet Board ethernet Tracy FIFO LatticeSCM Evaluation Board SWITCHES Out pins, LED’s

17. NIKHEF 27 Feb 2007RELAXd Serial Readout Status17 Current Test Setup: LatticeSC Evaluation Board + Medipix (one chip)

18. NIKHEF 27 Feb 2007RELAXd Serial Readout Status18

19. NIKHEF 27 Feb 2007RELAXd Serial Readout Status19

20. NIKHEF 27 Feb 2007RELAXd Serial Readout Status20 Measured speed without errors FPGA I/O only: > 532 MHz (higher not tested yet), Master-Slave 2.66 Gbit/s; Medipix 2.1: Fast Shift Register – 266 MHz (FSR test mode) Set/Read matrix – 83 MHz ok (100 MHz with a data shift in bits 0 of pixel row 0 and errors in the last pixel column) ; Medipix MXR (with default DAC settings): FSR – 166 MHz (matrix setting mode) S/R matrix – 100 MHz ok, 166 MHz with errors in the last or first column; should be faster when better DAQ (lvds) settings loaded (not tested yet)  fast 8b/10b serial link and communication between Lattice SC FPGA and Medipix work.

21. NIKHEF 27 Feb 2007RELAXd Serial Readout Status21 FPGA SC25 Eval Board Utilization

22. NIKHEF 27 Feb 2007RELAXd Serial Readout Status22

23. NIKHEF 27 Feb 2007RELAXd Serial Readout Status23

24. NIKHEF 27 Feb 2007RELAXd Serial Readout Status24 FPGA SC25 Eval Board Power Calculation

25. NIKHEF 27 Feb 2007RELAXd Serial Readout Status25 Lattice SC15 FPGA EPROM DACADC C SMASMA JTAGPWR C V-bias FLEX ? Standard serial < 3.4 Gbits/s 8b/10b (clock encoded in data) Lattice SC Evaluation board (“master”) ethernet Marvell ethernet board Planned Test Bench with Slave Board Slave board prototype

26. NIKHEF 27 Feb 2007RELAXd Serial Readout Status26 To Do: Designing the Slave board prototype and Quad chip carrier (see Bas v.d. Heijden talk) 10 Lattice SC15 Fpga’s already received (see pic); Connect the Lattice evaluation board with PC over ethernet via Marvell board and get FPGA-SDRAM interface running, so eval. board can be used as “master” for a slave board evaluation. (Marvell board already in our hands.) Complete the firmware for slave board. Test clock scheme using rx_clock from Master! PCS checksum, FIFO setup/hold time, SDR internal DAQ, external shutter Error handling etc.