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**Signal Integrity Analysis of Gigabit Interconnects**

Olie Kreidler Tektronix, Inc. Tektronix Confidential

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**Signal Integrity (SI): Digital Becomes Analog**

“At high frequencies … crosstalk and signal reflections can be perceived as logic triggers, and can be responsible for erroneous signal patterns” – EE Times, April 17, 1998, Special Section on Interconnects This quotation from a special section on interconnects in an April 1998 issue of Electronic Engineering Times summarizes what is happening as the industry moves to faster and faster clock speeds and data rates. Due to signal integrity problems, signals cross logic thresholds inadvertently, switching the digital receivers at the wrong times and causing bit errors. Tektronix Confidential

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**Industry Trends and Issues**

On-going trends and issues Trends: faster rise times, clock frequencies, increasing interconnect complexity Requirement: increasing need for signal integrity analysis and SPICE / IBIS interconnect modeling New trends and requirements Trends: S-parameters and eye diagrams are becoming part of compliance testing for passive PHY All standards currently are differential and serial Requirements Eye diagram and S-parameter compliance testing must be performed in differential mode Frequency dependent losses need to be modeled Tektronix Confidential

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**Outline Interconnect Measurement Accuracy Issues**

TDR/T and VNA Measurement Basics App Note: “TDR and VNA Measurement Primer” Impedance Measurements and IConnect® True Impedance Profile Time Domain S-parameter Measurements Eye Diagram Measurements TDR Probing and Fixturing Tektronix Confidential

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**High-Speed Serial Data Link Analysis The Measurement Challenge - A Closed Eye**

An “Open Eye” at the Transmitter a “Closed Eye” at the Receiver How to measure this eye? path + - Tx Rcv EQUALIZER + - Rcv The frequency-dependent loss in the interconnect causes the short data transitions, such as a …10101… sequence, to be attenuated much more than say a … …. sequence. In addition, different frequencies travel across the interconnect in slightly different speeds, thus smearing the fast edges. Intersymbol Interference (ISI) is commonly the term used to describe theses mechanisms which result in the time domain eye pattern becoming increasingly “closed” by jitter (DDJ). The risetime of the channel is relatively slow compared to the very fast 1’st channel. i.e. modern channel’s risetime is quite longer than the UI, thus the eye blures and ‘ISI’-s itself. 2007/06/10 Confidential V1.1

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**High-Speed Serial Data Link Analysis The Serial Data’s Solution to a Closed Eye**

An “Open Eye” at the Transmitter a “Closed Eye” at the Receiver Equalize it! path + - Tx Rcv EQUALIZER + - EQ. Rx + - Rcv Equalization is the answer for the digital receiver. The eye opens at the input of the receiver, the receiver can decode the signal. 2007/06/10 Confidential V1.1

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**This is now in your scope**

High-Speed Serial Data Link Analysis What should the Measurement do? - simple: do what your Tx/Rx does: implement equalization! An “Open Eye” at the Transmitter a “Closed Eye” at the Receiver Equalize it! path + - Tx Rcv EQUALIZER + - EQ. Rx + - Rcv Equalization is the answer to the eSerial receiver, so SW-implemented Equalization on the scope is also the answer to T&M. opens the eye for display (the scope-‘receiver’) Lets the user view ‘the inside’ of the Receiver This is now in your scope 2007/06/10 Confidential V1.1

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**Tek Solution DSA8200 with the TDR Module**

80E04 reflected rise time: 35 ps 80E10 reflected rise time 12ps / 15ps 8 acquisition channels 8-port TDR 4-port True Differential TDR Continuously stabilized rho and impedance waveforms All standard measurements available on rho and impedance waveforms The TDR waveform can be displayed in volts, rho (reflection coefficient) or ohms. When displaying rho or ohms, the instrument monitors the incident step amplitude and offset, and then uses continuously updated values in the calculation. This improves stability and repeatability of the measurement. Measurements and math waveforms correctly preserve the units and operate on rho and impedance waveforms like any other waveform. (This is not true on some other scopes) The can be very useful in that is allows the mean measurement over a gated zone as well as min and max values. DSP filtering is available to slow the rise time to match the DUT system rise time Tek has the fastest sample rate. And, since the step source is truly differential acquisition does not slow down with differential TDR The open Windows environment allows external analysis software such as LabView, Matlab or IConnect to run on the instrument. Tektronix Confidential

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**TDR Overview - Typical System**

4/20/2017 TDR Overview - Typical System Reflection Incident Sampler Reflections Incident Step Incident Step Probe 50 W 50 W Impedance reference t = 0 (1) Step generator source drives a baseline prior to t=0. (2) Step generator transitions at t=0 by opening switch and cutting off current in this leg. (3) Incident edge begins propagating toward back termination and toward DUT. Impedance reference establishes Z0 level. (4) Characteristic back termination doesn’t reflect energy back out toward DUT. (5) DUT reflects some of incident edge. (6) Sampler sees the following in this order: incident edge reflections off DUT from near end reflections off DUT from far end Test device Test device Step Generator

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**TDR Waveform Characteristics**

4/20/2017 TDR Waveform Characteristics TDR systems observe the superposition of incident and reflected signals at source Time separation t1-t0 assures ability to discern difference Superposition is normally regarded as a powerful circuit analysis tool that applies to lumped circuits. It also works for distributed systems, and TDR systems. The incident and reflected TDR information is displayed as superimposed vertically but time separated signals. Time t0 t1

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**TDR Rho Units Definition**

4/20/2017 TDR Rho Units Definition Amplitude + 1 0 Characteristic (Z = Z0) TDR r units are a convenience invented to allow arbitrary definition of unity incident signal amplitude. - 1 Time t0 t1

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**KCL Applied at r Discontinuity**

4/20/2017 KCL Applied at r Discontinuity Transmission lines support propagation with specific characteristic impedance Z Reflected and forward propagating signals will be such that Si = 0 is satisfied at discontinuity Can easily solve for Z knowing r, Z0, and KCL for lumped circuits Forward Incident Z0 Step Source (Z = Z0) The behavior of signals in a TDR system can be predicted from Kirchoff’s Current Law at the DUT attach node, considering only the immediately adjacent impedances. Discontinuity Reflected

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**Solution for Z Units Where**

4/20/2017 Solution for Z Units Where Z0 is the known reference impedance the sampling oscilloscope directly measures r Z is the calculated test device impedance Note textbooks usually show reversed expression:

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**TDR Waveforms - Simple Cases**

4/20/2017 TDR Waveforms - Simple Cases Waveforms with Open, Short and 50 terminations Amplitude + 1 Open (Z =) rreflected =+1 0 (Z = 50) The well known TDR signatures are a short, a characteristic termination, and an open. Knowledge of the behavior with these easily replicated boundary conditions allows calibration of a TDR system. rincident=+1 rreflected =-1 - 1 Short (Z = 0) Time t0 t1

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**TDS Measurement Basics TDR Block Diagram**

In a simple TDR setup, shown on this slide, the incident waveform amplitude at the Device Under Test (DUT) is typically half the original stimulus amplitude V at the TDR source. The smaller DUT incident waveform amplitude is due to the resistive divider effect between the 50 Ohm resistance of the source and 50 Ohm impedance of the coaxial cables connecting the TDR sampling head and the DUT. The impedance of the board trace can be determined from the waveform measured by the TDR oscilloscope, Vmeasured, which is the superposition of the incident waveform at the DUT and the reflected one, offset by 2 electrical lengths of the cable interconnecting the oscilloscope TDR sampling head to the DUT. Visually, a TDR waveform for an open circuit termination will reach the full amplitude of the original TDR step after 2 roundtrip delays from the TDR sampling head to the open termination. A short-circuit termination will be represented by a waveform that goes to 0 V, whereas a matching termination (50 Ohm) will stay at half the initial step voltage. Impedances with values that are between open and 50 Ohm, and 50 Ohm and short (0 Ohm) will be represented accordingly. A reader can immediately notice that there is more resolution for computing termination values between short (0 Ohm) and 50 Ohm than there is between 50 Ohm and open. Tektronix Confidential

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**TDR Measurements Basics Inductance and Capacitance Analysis**

This visual analysis has been used by TDR users for years. The same analysis can be applied not only qualitatively, but also quantitatively. Tektronix Confidential

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**Measurement Tools: Z-line Z-line-Based Measurements**

Inductance and capacitance of a via, for example, can be computed from the impedance profile using these equations. Tektronix Confidential

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**TDR Measurements Basics TDR Rise Time and Resolution**

Accepted rule of thumb for resolving two discontinuities 80E04 TDR rise time: 30-40ps at the end of the cable, probe, fixture Base 1/2trise resolution: 15-20ps 0.1”-0.12” in FR4 80E10 TDR rise time: 12-16ps at the end of the cable, probe, fixture Base 1/2trise resolution: 6-8ps 0.04”-0.048” in FR4 Two discontinuities will be observed as two separate ones if the distance between them is at least half the TDR rise time. There is no similar rule for how small a single discontinuity can be, but such discontinuity can not be much smaller that half the TDR rise time until it can no longer be resolved. Nonetheless, smaller discontinuities can be analyzed and electrically characterized, but you will need to do relative or comparative TDR measurements, as described in our application notes on electrical characterization of packages, connectors and sockets, and on package failure analysis. Go to and download our application notes to learn more. Tektronix Confidential

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**TDR Measurements Basics TDR Rise Time and Resolution**

More real case: resolving a single discontinuity Going beyond the TDR resolution and risetime: relative techniques Signal integrity modeling – JEDEC standard Failure analysis – golden device comparisons Two discontinuities will be observed as two separate ones if the distance between them is at least half the TDR rise time. There is no similar rule for how small a single discontinuity can be, but such discontinuity can not be much smaller that half the TDR rise time until it can no longer be resolved. Nonetheless, smaller discontinuities can be analyzed and electrically characterized, but you will need to do relative or comparative TDR measurements, as described in our application notes on electrical characterization of packages, connectors and sockets, and on package failure analysis. Go to and download our application notes to learn more. Tektronix Confidential

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**TDR Measurements Basics TDR Rise Time and Resolution**

If ps (or 12 ps) fast TDR rise time does not resolve it …. How in the world a 80 ps signal rise time will???????????? Conclusion: for SI analysis, use the actual DUT rise time! (filter down the rise time, if necessary) Tektronix Confidential

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**TDR Measurements Basics Differential TDR**

Differential serial link analysis Virtual ground plane Even and odd mode measurements Differential TDR measurements can come in handy when it is difficult to achieve good reference to a ground plane, or when a differential line analysis must be performed. A virtual ground plane, created by two TDR sources of opposite polarity, arriving simultaneously at a device under test with clear symmetry, helps achieve the desired measurement results. Tektronix Confidential

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**TDR Measurements Basics Good Measurement Practices**

Perform calibration routines regularly Minimum warm-up time 20 minutes Maintain constant temperature in the lab and check the instrument t° Zoom in on the DUT – but include all the DUT signature transitions (more to follow) Use torque wrenches when mating SMA or other RF connectors To obtain good quality impedance, signal integrity modeling, and failure analysis data, it is important to follow general good measurement practices when using a TDR oscilloscope. The instrument should be turned on and its internal temperature should be allowed to stabilize for minutes before performing any measurements. Calibration, compensation and normalization for the instrument must be performed regularly, as specified by the instrument manufacturer. The internal instrument temperature must be within the specified range from the calibration points for the given instrument. To maximize the resolution of the scope, in particularly in the time axis, it is important to zoom in on the DUT – but at the same time to allow a window that is sufficiently long to include all the reflections related to the DUT. The window that is too short may prevent the designer from obtaining complete and accurate information about the DUT. It is critical to use a torque wrench when mating any two connectors in your probing, cabling and fixturing setup. Such torque wrenches ensure a repeatable connection between the connectors, thus providing better measurement repeatability. These torque wrenches are available from most TDR manufacturers and many microwave component suppliers. It is also important to clean the RF connectors used in the probing / fixturing setup with isopropyl alcohol and lint free swab. Tektronix Confidential

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**Time and Frequency Domains VNA Block Diagram**

VNA: Vector Network Analyzer Similar diagram can be drawn for reverse measurements (port 2 to port 1) Differential VNA: 4-port measurements Time Domain Reflectometry measurements have always been the measurement approach of choice for board characterization work. Based on TDR measurements, a circuit board designer can determine characteristic impedances of board traces, compute accurate models for board components, and predict board performance more accurately. In a simple TDR setup, shown on this slide, incident waveform amplitude at the Device Under Test (DUT) is typically half the original stimulus amplitude V at the TDR source. The smaller DUT incident waveform amplitude is due to the resistive divider effect between the 50 W resistance of the source and 50 W impedance of the coaxial cables connecting the TDR sampling head and the DUT. The impedance of the board trace can be determined from the waveform measured by the TDR oscilloscope, Vmeasured, which is the superposition of the incident waveform at the DUT and the reflected one, offset by 2 electrical lengths of the cable interconnecting the oscilloscope TDR sampling head to the DUT. Please note that in reality TDR source is a more of current source. This fine point can make it more obvious the effects that DC loading of the termination may have on the incident step amplitude. Tektronix Confidential

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**Time and Frequency Domains Equations for TDR vs. VNA**

Traditionally, the impedance of the board is computed from TDR measurements using an equation that relates the DUT impedance to the impedance of the cable interconnecting the TDR oscilloscope sampling head to the DUT (equation 1). The reflection coefficient can be computed and displayed by a TDR oscilloscope. The equation (1) can be rewritten in terms of incident and reflected waveforms, or can include the waveform actually measured at the input of the oscilloscope TDR sampling head. The equation 3 listed here can be used to compute the impedance of the DUT Tektronix Confidential

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**Time and Frequency Domains TDR vs. VNA**

TDNA (Time Domain Network Analysis) Based on TDR/T measurements: Transient Broadband More intuitive for a digital designer Dynamic range: about 50-60dB Less expensive FDNA (Frequency Domain Network Analysis) Based on VNA measurements: Steady-state measurements Narrow-band More intuitive for microwave/RF designer More expensive Higher dynamic range (up to 110 dB) There are definite advantages to both TDR/TDNA and VNA for interconnect measurements. With TDR, one can see transients as they occur in time in electric sense (space in conventional sense). Unwanted reflections can be windowed out, and one can focus on those reflections that are of interest at the moment. The broadband nature of TDR should allow faster automatic measurement processing if such a need arises. They are more intuitive to a digital designer, who, we believe, are the majority of the interconnect characterization people these days. And, last but not least, a time domain measurement system is typically less expensive than a comparable VNA-based system. VNA, on the other hand, focuses on steady-state measurements, after all the reflections occur and settled. Granted, it can display TDR-like waveforms reconstructed based on frequency domain measurements. It is very narrowband, and each point is acquired separately. It is a common tool for an RF/microwave designer, and as such is more intuitive for them. Both system can be used very successfully. Our choice is Time Domain system, because of smaller expense that a characterization engineer need to set-up a characterization lab, because of the windowing and being more intuitive, for a majority of people who do characterization Tektronix Confidential

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**Time and Frequency Domains Time or Frequency Domain?**

SI measurements do not require high dynamic range Compliance testing does not require high DR About –10 dB for insertion loss -25 to –35 dB for return loss Higher for frequency domain crosstalk For digital designs, having a time-domain match is more important than having a broadband frequency-domain match. This is why we do our extraction in the time domain. The weighting or importance of the match at every frequency is not equal, because not all frequencies are equally represented in a digital step. This is part of what you see in the frequency domain discrepancy -- those high-frequency components are not present heavily enough in the step to cause significant error. If there is agreement in the time domain, that is sufficient. Analyzing the properties of interconnects, we begin to realize that TDR is the natural methodology for interconnect analysis and characterization work. We typically require a model for an interconnect that includes more than one element. Interconnects are broadband structures, that is they are designed to carry broadband digital signals. Measurement most commonly do not require signal to noise ratio or dynamic range of more than 30dB, easily achieved with TDR scopes; they are most commonly not resonant structures. But, interconnect measurements do require good time resolution to be able to observe small components of the interconnect system. Tektronix Confidential

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**Impedance Accuracy TDR Basic Equations**

Z V DUT incident reflected + - × = Traditionally, the impedance of the board is computed from TDR measurements using an equation that relates the DUT impedance to the impedance of the cable interconnecting the TDR oscilloscope sampling head to the DUT. The reflection coefficient can be computed and displayed by a TDR oscilloscope. This equation can be rewritten in terms of incident and reflected waveforms, or can include the waveform actually measured at the input of the oscilloscope TDR sampling head. The equation at the bottom of the slide can be used to compute the impedance of the DUT. Tektronix Confidential

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**Impedance Accuracy TDR Multiple Reflection Effects**

Issue: impedance accuracy suffers due to signal re-reflection inside the DUT We mentioned previously that TDR measurement accuracy suffers from the multiple reflection effects when multiple discontinuities are involved in the measurement. True impedance profile of the DUT can be obtained, however, through an inverse scattering algorithm reported by several authors. Based on the incident step and TDR response of the system, the multiple reflections can be dynamically deconvolved from TDR response; because of that, another name used for this algorithm is “dynamic deconvolution.” Tektronix Confidential

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**Impedance Accuracy IConnect Computation of the True Impedance Profile**

This is the mathematical description of the multiple reflection effects in the DUT; this matrix needs to be solved in order to obtain the true impedance profile for the DUT. Tektronix Confidential

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**Impedance Accuracy Board Trace IConnect® Z-line**

Multiple reflections in TDR waveform Scope reads here about 44 Ohm instead of 50 Ohm To compute the impedance profile waveform, both the incident and reflected waveforms must be known. The reflected waveform is the TDR measurement of the DUT. The incident waveform, on the other hand, can be computed in several ways. The easiest is to compute it from an acquired reference short or open waveform, where a short or open termination is connected at the interface between the instrument cables (probes) and the DUT, in place of a DUT. A short termination typically has less reactance, but an open termination can be easier to measure repeatably. The green line is the DUT TDR waveform; by observing this waveform alone, one could conclude that it represents a series of transmission lines of different impedance, going through multiple discontinuities on the board. The reality is, however, that there is only one nominally 25 Ohm line involved, surrounded by two very short 50 Ohm lines, and terminated at the far end with an open. The true impedance profile (blue waveform), computed by TDA Systems’ IConnect® software automatically, immediately shows the correct impedance profile of the DUT structure; the actually impedance of the middle section is 26.9 Ohm, as displayed by a cursor impedance readout. Tektronix Confidential

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**Impedance Accuracy Board Trace IConnect® Z-line**

Accurate impedance profile in IConnect® To compute the impedance profile waveform, both the incident and reflected waveforms must be known. The reflected waveform is the TDR measurement of the DUT. The incident waveform, on the other hand, can be computed in several ways. The easiest is to compute it from an acquired reference short or open waveform, where a short or open termination is connected at the interface between the instrument cables (probes) and the DUT, in place of a DUT. A short termination typically has less reactance, but an open termination can be easier to measure repeatably. The green line is the DUT TDR waveform; by observing this waveform alone, one could conclude that it represents a series of transmission lines of different impedance, going through multiple discontinuities on the board. The reality is, however, that there is only one nominally 25 Ohm line involved, surrounded by two very short 50 Ohm lines, and terminated at the far end with an open. The true impedance profile (blue waveform), computed by TDA Systems’ IConnect® software automatically, immediately shows the correct impedance profile of the DUT structure; the actually impedance of the middle section is 26.9 Ohm, as displayed by a cursor impedance readout. Tektronix Confidential

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**Impedance Accuracy Package Trace IConnect® Z-line**

Raw TDR: confusing multiple reflections Impedance profile in IConnect®: Exact failure location, improved resolution To compute the impedance profile waveform, both the incident and reflected waveforms must be known. The reflected waveform is the TDR measurement of the DUT. The incident waveform, on the other hand, can be computed in several ways. The easiest is to compute it from an acquired reference short or open waveform, where a short or open termination is connected at the interface between the instrument cables (probes) and the DUT, in place of a DUT. A short termination typically has less reactance, but an open termination can be easier to measure repeatably. The green line is the DUT TDR waveform; by observing this waveform alone, one could conclude that it represents a series of transmission lines of different impedance, going through multiple discontinuities on the board. The reality is, however, that there is only one nominally 25 Ohm line involved, surrounded by two very short 50 Ohm lines, and terminated at the far end with an open. The true impedance profile (blue waveform), computed by TDA Systems’ IConnect® software automatically, immediately shows the correct impedance profile of the DUT structure; the actually impedance of the middle section is 26.9 Ohm, as displayed by a cursor impedance readout. Tektronix Confidential

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**Impedance Accuracy IConnect® Software Z-line Algorithm**

TDR measurements suffer from multiple reflections No limited to TDR, also in TD in VNA IConnect removes multiple reflections Ensures accurate impedance measurements in multi-impedance DUT Direct and accurate readout of Z, td, L, C Different and more accurate than Z readout in the scope Attention!: Data noise may interfere with accuracy Use scope averaging Use software noise filtering Line loss is extracted separately The Z-line algorithm, implemented in IConnect TDR software, removes the multiple reflections and computes the true impedance profile from the TDR profile measured by a TDR oscilloscopes. The true impedance profile gives us accurate impedance measurements; but, even more importantly, it allows easy interconnect model generation. Being a computational algorithm, however, Zline suffers from a general problem of “garbage in – garbage out.” This means that only accurate TDR measurement will allow the designer to compute an accurate impedance profile; this is why we spend significant time in this presentation on helping the attendees understand the accuracy issue of the TDR measurements. Additionally, there is a software noise filtering mechanism in IConnect, called “threshold,” which effectively removes the noise from the TDR waveform. The higher the threshold level, the more noise will be filtered, up to the point when the filtering will begin to remove meaningful data from the TDR waveform. Normal operating range for the threshold parameter is between 15% and 85%. Finally, impedance deconvolution algorithm does not recover the rise time degradation and resulting loss of resolution in the TDR waveform due to losses in the DUT and the RLC filter effect resulting from the loss interaction with the inductive and capacitive discontinuities. If the losses per unit length in the DUT are significant and the DUT is electrically long, after some length in the DUT it may not be possible to resolve small discontinuities in the signal path. Additional TDR measurement tricks and techniques may need to be utilized to observe and model these smaller discontinuities hidden by loss in the DUT. Tektronix Confidential

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**Frequency Dependent S-parameters Why S-parameters**

Compliance testing Insertion loss (around 6-10 dB) Return loss (around dB) Frequency domain crosstalk Link performance evaluation and simulation Simulate S-parameters directly Insertion and return loss, frequency dependent crosstalk, have become an important requirement for specification compliance testing – and so has the eye diagram mask test. The mask diagram test initially was used in communication standards, but now is commonly use in new serial link standard compliance testing procedures. Tektronix Confidential

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**Frequency Dependent S-parameters Equations for TDR vs. VNA**

Traditionally, the impedance of the board is computed from TDR measurements using an equation that relates the DUT impedance to the impedance of the cable interconnecting the TDR oscilloscope sampling head to the DUT (equation 1). The reflection coefficient can be computed and displayed by a TDR oscilloscope. The equation (1) can be rewritten in terms of incident and reflected waveforms, or can include the waveform actually measured at the input of the oscilloscope TDR sampling head. The equation 3 listed here can be used to compute the impedance of the DUT Tektronix Confidential

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**Frequency Dependent S-parameters Single-ended TDR**

Tektronix Confidential

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**Frequency Dependent S-parameters Correct Data Acquisition**

DUT waveform to settle to steady DC level Tektronix Confidential

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**Frequency Dependent S-parameters Return Loss = TDR**

Measure TDR, compute S11 (return loss) in IConnect What is wrong with this RL picture? Tektronix Confidential

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**Frequency Dependent S-parameters Insertion Loss = TDT**

Measure TDT, compute S21 (insertion loss) in IConnect Test case for loss extraction Tektronix Confidential

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**Frequency Dependent S-parameters Differential and Mixed S-parameters**

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**Frequency Dependent S-parameters Differential TDR = S11diff**

Several InfiniBand traces of different length. Differential return loss. Tektronix Confidential

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**Demo of TDR and S parameter measurements**

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Additional Material Tektronix Confidential

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**Tektronix Confidential**

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**Frequency Dependent S-parameters Power Plane Resonance**

Observe plane impedance profile (Z-line) Resonances between planes Tektronix Confidential

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**Frequency Dependent S-parameters Electrical Compliance Testing**

Need fixture to interface to interconnects for compliance testing DUT Connection Traces Reference thru Traces Infiniband Connector Tektronix Confidential

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**Frequency Dependent S-parameters VNA Fixture De-embedding**

For VNA requires additional standard to de-embed properly Insertion loss: fixture insertion loss must be subtracted from DUT insertion loss Return loss: no way to de-embed without additional standards! Fixture return loss ends up being lumped with the DUT return loss Can be a problem even with quality fixtures Tektronix Confidential

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**Frequency Dependent S-parameters VNA Real Fixture Limitation Example**

Spec: -10 dB at 1.25 GHz With fixture, the cable assembly is failing the spec! Fixture is failing the assembly with VNA measurements Tektronix Confidential

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**Frequency Dependent S-parameters TD-VNA Fixture De-embedding**

Simplicity of calibration allows simple fixture de-embedding Spec: -10 dB at 1.25 GHz Fixture de-embedded with TDNA, the assembly is passing Tektronix Confidential

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**Frequency Dependent S-parameters Correlation with Network Analyzer**

Tektronix Confidential

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**Frequency Dependent S-parameters Correlation with Network Analyzer**

Tektronix Confidential

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**Frequency Dependent S-parameters Correlation with Network Analyzer**

Tektronix Confidential

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**The TD-VNA bandwidth is directly related to TDR/T rise time**

Frequency Dependent S-parameters Correlation with Network Analyzer: 65 GHz The TD-VNA bandwidth is directly related to TDR/T rise time These data were measured using the PSPL Model 4022 and a 70 GHz sampler S-parameters correlate to 65 GHz Courtesy: Kipp Schoen, Picosecond Pulse Labs Tektronix Confidential

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**Frequency Dependent S-parameters Calibrated Results: SOLT**

Dashed line – Tektronix with SOLT cal Solid line – Agilent 8510 VNA Excellent correlation between TDNA and FDNA data Tektronix Confidential

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**Frequency Dependent S-parameters Noise Floor and Dynamic Range**

To reduce noise floor: Increase number of averages Navg Increase number of points Npoints Decrease acquisition window length (increase effective incident power) The noise floor in the system can be lowered and correspondingly the Signal-to-Noise Ratio (SNR) of the system for the given bandwidth can be improved by increasing the number of averages or the number of points in the acquisition window. Moreover, increasing the number of averages or number of points n times we increase the SNR by a factor described in the equation above, where N is the number of points and Navg is the number of averages in the acquisition settings. This is referred to as a processing gain To further improve SNR of the system we can keep the acquisition window short, thereby increasing the effective power of the stimulus signal. The dynamic range is a parameter normally characterizing the frequency domain measurements. On the other hand, the EA-TDR measurements are made in time domain. However, in order to analyze the precision of the EA-TDR/T measurements it is useful to estimate how accurately we recover the parameters for our DUT from the frequency domain point of view. The dynamic range that is of interest to us is the system dynamic range. It is defined as the difference between the reference (or stimulus) power in the measurement system and the noise floor of the system for a given frequency Tektronix Confidential

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**Frequency Dependent S-parameters TD-VNA Incident Effective Power**

The TD-VNA bandwidth directly related to the risetime of the TDR and TDT signals ps TDR 25 ps Tektronix Confidential

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**Frequency Dependent S-parameters TD-VNA Dynamic Range (with PSPL Module)**

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**Frequency Dependent S-parameters IConnect Produces S-parameters**

Differential, mixed mode and single ended Insertion, return loss and frequency domain crosstalk Performance with base DSA8200: dB dynamic range (vs. 100 dB for VNA), 12 GHz bandwidth Performance with 80E10 up to 50GHz bandwidth Cost ½ of a comparable VNA solution Intuitive, easy to use and more than adequate dynamic range for digital designers Tektronix Confidential

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**Minimal calibration required**

TDT and IConnect Eye Diagram Efficient S-parameters Testing in IConnect Easy, quick, efficient S-parameter measurements and electrical compliance testing Insertion, return loss, frequency dependent crosstalk Excellent correlation with traditional VNA techniques Cost-effective and quick Minimal calibration required Only reference at the end of the fixture Easy fixture de-embedding Tektronix Confidential

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**TDT and IConnect Eye Diagram Why Eye Diagram in IConnect?**

Eye Diagram for Interconnects Specification mask testing Not just communication standards, also for new serial link standards IConnect benefit: no pattern generator required for interconnect eye diagram analysis De-embed deterministic / interconnect jitter No active component jitter Insertion and return loss, frequency dependent crosstalk, have become an important requirement for specification compliance testing – and so has the eye diagram mask test. The mask diagram test initially was used in communication standards, but now is commonly use in new serial link standard compliance testing procedures. Tektronix Confidential

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**TDT and IConnect Eye Diagram Eye Diagram Degradation in Interconnects**

Interconnect losses Pattern-dependent, crosstalk induced jitter Method to improve the eye Equalization, pre-emphasis and de-emphasis Other signal conditioning techniques Only deterministic jitter exists in interconnects, no random component! Time Domain Reflection and Transmission (TDR/T) measurement based eye diagram is computed in IConnect TDR software using Fourier techniques to compute the convolution of an input with the measured system response function. The modeling assumptions that go into this type of computation are that the system is linear and time-invariant, which are pretty standard assumptions for all interconnect modeling. The modeling equations can be found in a digital signal processing textbook (e.g., Discrete-Time Signal Processing by Oppenheim and Schafer). A time domain transmission waveform through the DUT is required for direct eye diagram prediction from the measurement. Alternatively, the eye can be predicted based on the models extracted for the interconnect, by simulating the transmission through the interconnect, and using it for the eye diagram prediction. The user can choose between several different stimuli patterns, pattern length, signal amplitude, speed and rise time. Custom pattern can be entered as well. Tektronix Confidential

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**TDT and IConnect Eye Diagram Eye Diagram Options**

TDT easily gives the eye diagram degradation Deterministic jitter only The user can choose between several different stimuli patterns, pattern length, signal amplitude, speed and rise time. Custom pattern can be entered as well. Tektronix Confidential

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**TDT and IConnect Eye Diagram New Eye Mask and Jitter Measurements**

Tektronix Confidential

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**TDT and IConnect Eye Diagram Why is TDT Based Eye Better?**

Easy to de-embed fixture The same improvement as for S-parameter measurements! No jitter from the pattern generator Tektronix Confidential

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**TDT and IConnect Eye Diagram Predicted and Measured Eye Diagrams**

Pattern Generator Based IConnect K28.5 IConnect PRBS 210-1 Tektronix Confidential

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**TDT and IConnect Eye Diagram Predicted and Measured Eye Diagrams**

2^10-1 pattern generator measurement 2^10-1 IConnect eye from TDT measurement Data Courtesy FCI Electronics Tektronix Confidential

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**TDT and IConnect Eye Diagram Predicted and Measured Eye Diagrams**

1.5Gb/s (Gen 1) 6.0Gb/s (Gen 3) 3.0Gb/s (Gen 2) Serial ATA data courtesy Molex, Inc. And here is another example, illustrating correlation between the pattern generator measured eye and the eye predicted in IConnect from TDT measurements, for a serial ATA example. Again, good correlation is observed. Tektronix Confidential

68
**TDT and IConnect Eye Diagram Efficient Eye Diagram Testing in IConnect**

Easy, quick, efficient eye diagram measurements and compliance testing Excellent correlation with traditional pattern generator techniques Cost-effective and quick Minimal calibration required Only reference at the end of the fixture Easy fixture de-embedding Tektronix Confidential

69
**Outline Interconnect Measurement Accuracy Issues**

TDR/T Probing and Fixturing App Note: “TDR Measurement Primer” App Note: “TDR Techniques for Characterization and Modeling of Electronic Packaging” Quick Guide:“Interconnect Probing Quick Guide” Interconnect SPICE / IBIS Modeling and Model Validation Tektronix Confidential

70
**Probing and Fixturing TDR Measurement Setup**

TDR probe with signal and ground connection TDR oscilloscope Time Domain Reflectometry measurements have always been the measurement approach of choice for board characterization work. Based on TDR measurements, a circuit board designer can determine characteristic impedances of board traces, compute accurate models for board components, and predict board performance more accurately. Tektronix Confidential

71
**Probing and Fixturing Probing and Fixturing Issues**

Probing is the weakest link! Start with a probe 50 Ohm for TDR measurements must be rugged and inexpensive ensure stable repeatable contact large pitch* means small bandwidth variable pitch means poor repeatability ensure sufficient compliance Board and package level probing solutions have not been developed to the same degree as the on-wafer probing. Because of that, in the overall measurement system, probing often becomes the weakest link, not matching the performance of the measurement equipment. Some of the characteristics of a good probe are given on this slide. 50 Ohms is the standard reference impedance used in TDR instrumentation, and using a probe of different impedance will distort the results. Large probe pitches are sometimes required by the DUT, but these probes will have a large parasitic inductance, which results in lower bandwidth. Compliance is often a challenge for a high-performance narrow-pitch probe, but can be more easily achieved with a larger pitch probe. This represents a typical trade-off between mechanical and electrical performance of a probe. * Pitch: center-to-center signal to ground pad spacing Tektronix Confidential

72
**Probing and Fixturing Package and Connector Probing**

Use a high-quality probe (and positioner) Need an interface adapter or fixture to probe Fixturing requirements Reproduce the real application environment Ensure easy fixture de-embedding (reference short and open structures may be needed) Because of the number of issues that emerge when probing an IC package, the right answer appears to be: fixture it up, de-embed the fixture and use high-performance microwave probe (which allows 20-40Ghz bandwidth). Make sure your fixture does not decrease the bandwidth of the measurement path. For some type of package and some measurements a direct contact with a microwave probe is possible; other measurements (e.g., testing in deep cavity inside a package) may not allow such direct contact. These pictures provide some samples of the package fixtures that can be used for electrical characterization of packages using TDR. Tektronix Confidential

73
**Probing and Fixturing Board Probing**

Ensure good contact to a via Difficult for a microwave probe Use TDA’s QuickTDR™ probe Probes also available from TDR manufacturers Ensure ground contacts near your signals Variable pitch: a sad necessity Available from from TDR manufacturers and probe manufacturers (Cascade Microtech, ICM) Measurements suffer from poor repeatability and decrease the instrument usable bandwidth For boards, microwave probe often fails to make good contact on available pads. If the measurement requirement is limited to a 2-4 Ghz, the semirigid coax type of probe may be the best approach. If higher measurement bandwidth is desired, special arrangement for contact pads that will accommodate a high performance probe must be made. Variable pitch probe severely limits accuracy and reproducibility of the measurements. Positioners and probing stations must accommodate the appropriate board size, which sometimes can be quite large. Tektronix Confidential

74
**Probing and Fixturing Probing vs. Fixturing**

Probing advantages: Maximum flexibility for multiple device measurements No fixture de-embedding required But: Requires DUT to have easily accessible contact areas Positioning system may be expensive Fixturing advantages: Evaluate the DUT in its intended environment of use (example: package on a board) Great flexibility for specific DUT But: Difficult to change after the fixture has been designed Must de-embed fixturing from measurements The bottom line in the comparison between probing and fixturing is that these approaches are complimentary. For example, even if you are designing a board, you should make sure that there are ground contacts available close to where you plan to probe your high-speed signals; we will consider such forethought a form of fixturing. The forethought that goes into enabling you to deliver your high-speed TDR signals to the DUT and back is what fixturing is all about. These approaches are complementary! Fixturing is thinking ahead about how you will probe! Tektronix Confidential

75
**Outline Interconnect Measurement Accuracy Issues**

Impedance, S-parameters and eye diagram measurements and compliance testing Interconnect SPICE / IBIS Modeling and Model Validation Z-line, lossy line, and automatic behavioral modeling Tektronix Confidential

76
**Outline Interconnect Measurement Accuracy Issues**

Interconnect SPICE / IBIS Modeling and Model Validation Measurement Based Interconnect Analysis Behavioral Modeling: MeasureXtractor™ Topological Modeling: TDT and Lossy Line Modeling Impedance Profile (Z-line) Transmission Line Modeling L and C JEDEC computation Examples: Power Plane Analysis Backplanes and cable assemblies Tektronix Confidential

77
**Measurement-Based Link Design How to Analyze System Signal Integrity?**

Is this similar to your application? These interconnect models can be extracted using a number of pre-layout analysis and electromagnetic field solver tools. However, “it is paramount to compare the model with real measurements,”. The system prototype must be manufactured, (unless a test board prototype has been manufactured and characterized beforehand), and with these prototypes in hand, the designer will verify the accuracy of the pre-layout analysis tool assumptions using real-life measurements and modeling. It is these real-life measurement and modeling techniques that we will focus on in this paper. Deterministic jitter and eye diagram degradation are caused by transmission line frequency dependent losses and crosstalk, and therefore must be modeled using coupled and lossy transmission line models. Signal distortion and digital switching errors result from crosstalk, reflections and ringing. Modeling the crosstalk requires the coupled line modeling techniques. Understanding reflections demands increased impedance measurement accuracy and transmission line modeling. Predicting signal ringing requires understanding of interaction between the lumped (RLC) and distributed (transmission line) elements in the system. All the interconnect models – lumped and distributed, lossy and coupled – can be extracted using modeling techniques based on Time Domain Reflectometry (TDR) and Transmission (TDR/T) measurements. A TDR oscilloscope, coupled with IConnect® TDR-based software modeling tools, becomes a powerful system for interconnect impedance measurements, signal integrity SPICE and IBIS modeling, and pre-layout and field solver model validation. App Note: “Signal Integrity Modeling of Gigabit Backplanes, Cables and Connectors Using TDR” Tektronix Confidential

78
**Measurement-Based Link Design Interconnect Measurement Based Design**

Linearize the link input and termination for initial analysis Tektronix Confidential

79
**Measurement-Based Link Design Measurement Based Design Details**

Impedance measurement => reflections TDR/T or S-parameters => losses, jitter, eye diagram degradation System losses is a result of losses in components Eye diagram is a result of losses and crosstalk in components Tektronix Confidential

80
**IConnect Modeling Methodology Goals and Model Validity**

Goal: accurately predict interconnect performance via simulations Need an accurate SPICE /IBIS models Model required range of validity is defined by the fast corner rise time of the driver Equivalent bandwidth estimated as: fbw=0.35 / trise or harmonics of clock It may be desired to extend the required range of model validity beyond trise and fbw Have a confidence guard band Our goal is to obtain a SPICE model that will enable us to predict the interconnect performance. Clearly, if we can ignore the signal integrity issues in interconnects, life will be easy. However, if we can’t ignore these issues, we need to model the interconnects and to include the interconnect models in simulations. In addition, it is important to remember that the model must be valid within a certain frequency range, as defined by the signals in the digital system. Tektronix Confidential

81
**IConnect Modeling Methodology Modeling Technique: Behavioral**

Behavioral Modeling: MeasureXtractor™ A universal, fully automatic, exact modeling technique Can use time or frequency domain data Matches exactly both time and frequency response Perfect for… Connector, package or socket modeling Model for a characterization fixture for a connector, a package or a cable Model for a daughtercard board When behavioral model is acceptable Can create large model for a large interconnect such as a backplane or cable assembly Tektronix Confidential

82
**IConnect Modeling Methodology Modeling Technique: Topological**

Lossy line and coupled lossy line modeling When need to predict losses and crosstalk Large lossy backplanes and motherboards Cables and cable assemblies Impedance profile (Z-line) models When losses are small Need to predict impedance reflections, crosstalk only Small daughtercards, boards Electrically long connectors, packages Tektronix Confidential

83
**IConnect Modeling Methodology Modeling Technique: Topological**

JEDEC technique for L and C computation Industry standard technique for electrically short interconnects Electrically short: trise >> tprop delay Packages, connectors, sockets trise tprop delay Tektronix Confidential

84
**IConnect Modeling Methodology Behavioral or Topological?**

Tektronix Confidential

85
**IConnect Modeling Methodology Methodology: Gbit Ethernet Example**

Launch, high-speed connector: Z-line modeling Cable and Test cards: lossy line modeling Any piece can be modeled in MeasureXtractor™ Lumped pieces can be modeled with JEDEC technique Tektronix Confidential

86
**TDR/T or VNA Measurements**

IConnect Modeling Methodology Measurement Based Approach SPICE TDR/T or VNA Measurements Extracted interconnect, instrument source models Direct link to simulators Automatic comparison of simulation and measurement in IConnect waveform viewer The measurement-based approach described here employs the Measure-Model-Verify philosophy. A prototype is measured using TDR techniques, and based on the acquired data, an equivalent circuit model is created. The model is verified through simulation, with the same excitation and termination used for simulation and measurement. The simulated and measured waveforms are then compared and the model is verified and adjusted if necessary. This measurement-based approach does not contradict with the design approach that utilizes analytical tools, such as electromagnetic field solvers. If the component design was based on an electromagnetic field solver analysis, a prototype must still be fabricated. At this point, the prototype must be carefully characterized and accurate models for the prototype generated. The Measure-Model-Verify approach, again in this case, can be used in order to ease the modeling work and create an accurate prototype model from measurements. If the measurement-based model differs from the original analytical model, then the difference between assumptions in the field solver and the measurement reality must be reconciled and the model representing the prototype, as it will be used in the actual system, must be defined. Tektronix Confidential

87
**Outline Interconnect Measurement Accuracy Issues**

Interconnect SPICE / IBIS Modeling and Model Validation Behavioral Modeling: MeasureXtractor™ Topological Modeling: TDT and Lossy Line Modeling Impedance Profile (Z-line) Transmission Line Modeling L and C JEDEC computation Examples: Power Plane Analysis Backplanes and cable assemblies Tektronix Confidential

88
**Behavioral Modeling MeasureXtractor™ Modeling**

A fully automatic algorithm for conversion of VNA S-parameter or TDR/T data into SPICE or IBIS model Passivity of the model guaranteed Compact and efficient Fully automated Not an optimization Behavioral models Tektronix Confidential

89
**Behavioral Modeling Lack of Passivity Produces Oscillations**

Slide courtesy: Instability is a very bad thing! TERASPEED CONSULTING GROUP Tektronix Confidential

90
**Behavioral Modeling Sources of Passivity Issues**

Insufficient attention to measurements or calibration Interconnects do not amplify signals! Even if individual measurements are passive, combined system measurements can have amplification properties Simulator extrapolation and interpolation based on model, not original measurement Finite measurement acquisition window (in the limit, the data is infinite!) Tektronix Confidential

91
**Behavioral Modeling Example: Correlation of Measurement and Model**

Exact correlation in time and frequency domains Tektronix Confidential

92
**Behavioral Modeling Example: Model Listing**

… .subckt DUT port1 gnd_ r1 port r2 port r3 port r4 port r5 port r6 port r7 port r8 port r9 port e+007 r10 port r11 port r12 port r13 port … r14 port r15 port r16 port r17 port r18 port r19 port r20 port r21 port r22 port r23 port r24 port r25 port r26 port r27 port … c33 34 gnd_ e-016 r90 35 gnd_ c34 35 gnd_ e-016 r r92 36 gnd_ c35 36 gnd_ e-016 r93 37 gnd_ c36 37 gnd_ e-016 r94 38 gnd_ c37 38 gnd_ e-015 r95 39 gnd_ c38 39 gnd_ e-014 .ends Tektronix Confidential

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**Behavioral Modeling MeasureXtractor™ Summary**

Converts S-parameters or TDR/T data into an exact-match model Passivity is guaranteed If you can measure it, and want model it with little effort, use MeasureXtractor™! Tektronix Confidential

94
**Outline Interconnect Measurement Accuracy Issues**

Interconnect SPICE / IBIS Modeling and Model Validation Topological Modeling: TDT and Lossy Line Modeling App Note: “Practical Characterization of Lossy Transmission Lines Using TDR” Impedance Profile (Z-line) Transmission Line Modeling L and C JEDEC computation Examples: Power Plane Analysis Backplanes and cable assemblies Tektronix Confidential

95
**TDT and IConnect Lossy Lines TDT and Lossy Line Modeling Is For:**

Long lossy transmission lines in backplanes and motherboards Long lossy cables Tektronix Confidential

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**TDT and IConnect Lossy Lines Loss Example: Time and Frequency Domain**

Tektronix Confidential

97
**TDT and IConnect Lossy Lines Skin Effect vs. Dielectric Loss**

Typical FR-4 50 Ohm Trace Skin effect will dominate the loss and dispersion characteristics of the lower gigahertz range, whereas the dielectric loss will dominate in the upper gigahertz range. For example, for 1oz copper, 8mil wide trace, er of 3.5 and tan(d) of 0.02 (typical FR4 trace of about 50 Ohm impedance), the dielectric loss will begin to dominate near 1Ghz Tektronix Confidential

98
**TDT and IConnect Lossy Lines Different Loss Modeling Approaches**

Lumped (behavioral) Defined for all frequencies Slow for long lines Distributed Based on parameters (Rskin, Gdielectric) Not as general Based on RLGC data General for quasi-TEM Not defined for all frequencies Tektronix Confidential

99
**TDT and IConnect Lossy Lines Causality in TEM Models**

From basic physics, the real and imaginary parts of the dielectric constant are tightly related to ensure causality. The same is true of the permeability constant, m In TEM modeling, this means that R and L are related, and G and C are related Models based on RLGC data (or S-parameters) should address this issue !!! Tektronix Confidential

100
**TDT and IConnect Lossy Lines Our Model Extraction Approach**

Assume standard simulator equations: Two extraction methods: Open circuit reflection (TDR, one port) Matched circuit transmission (TDR, TDT, two-port) Extract loss parameters: Rdc, Rac, Gdc, Gac, L, C Write resulting model in various formats Lumped Distributed with parameters Distributed with RLGC data Tektronix Confidential

101
**Extracted skin effect and dielectric loss parameters**

TDT and IConnect Lossy Lines Example: Extraction Results (Transmission) Extracted skin effect and dielectric loss parameters Simulated and measured transmission Tektronix Confidential

102
**TDT and IConnect Lossy Lines Symmetrical Lossy Coupled Line Model**

Assumptions: The lines are symmetrical TDR steps are symmetrical TDR steps arrive at the lines at the same time at the beginning of both lines If the lines are completely symmetric (example: differential lines on a board), a symmetric coupled line model can be used. The assumptions listed on this slide, however, must be met. Differential TDR measurements can come in handy when it is difficult to achieve a good ground plane reference, or when a differential line analysis must be performed. A virtual ground plane, created by two TDR sources of the same shape and opposite polarity arriving simultaneously at a DUT interface, helps achieve the desired measurement results. We mentioned previously that TDR measurement accuracy suffers from multiple reflection effects when multiple discontinuities are involved in the measurement. The true impedance profile of the DUT can be obtained, however, through the inverse scattering algorithm discussed above. Based on the incident step and TDR response of the system, the multiple reflections can be dynamically deconvolved from the TDR response. Tektronix Confidential

103
**IConnect Differential TDR Techniques Even/Odd vs. Common/Differential**

In some cases, the differential impedance alone is the parameter of interest to a board designer. Based on the differential impedance value, he or she can make first cut at predicting the propagation of the signal through the differential pair. In addition, the common mode impedance can help analyze the common mode noise rejection; if the common mode impedance is much higher than the differential impedance, the common mode rejection will be high. Note that for the case in which no coupling between the lines in the differential pair is present, both even- and odd-mode impedance values simply collapse to the characteristic impedance of each line. In most practical cases, the even and odd mode delays will also be different Tektronix Confidential

104
**Zeven>Zself>Zodd teven>tself>todd**

IConnect Differential TDR Techniques Even and Odd Impedance Profile Example Zeven>Zself>Zodd teven>tself>todd Even and odd analysis, based on even and odd impedance profiles, is an extremely useful TDR analysis tool for symmetric line systems such as differential lines on boards, cables, connectors, and BGA packages. The odd impedance profile is obtained from a differential TDR measurement with two TDR sources of opposite polarity, and the even impedance profile is obtained through a measurement with two TDR sources of the same polarity. A differential reference short is used for computing the impedance profile Note: - Odd mode = differential measurement (two TDR sources of opposite polarity) - Even mode = common mode measurement (two TDR sources of the same polarity) Tektronix Confidential

105
**TDT and IConnect Lossy Lines Example: Extraction Results (Reflection, Coupled)**

Both self and mutual parameters are extracted Tektronix Confidential

106
**Outline Interconnect Measurement Accuracy Issues**

Interconnect SPICE / IBIS Modeling and Model Validation Topological Modeling: Impedance Profile (Z-line) Transmission Line Modeling App Note: “PCB Interconnect Characterization from TDR Measurements” App Note: “Characterization of Differential Interconnect from TDR Measurements” L and C JEDEC computation Examples: Power Plane Analysis Backplanes and cable assemblies Tektronix Confidential

107
**Short (lossless) transmission lines **

IConnect Single-ended TDR Techniques Single Transmission Line Modeling Is For: Short (lossless) transmission lines Electrically long packages (longer than Trise) Electrically long connectors (longer than Trise) Tektronix Confidential

108
**IConnect Single-ended TDR Techniques Transmission Line Z and td**

Directly available from impedance profile Eliminate confusion about: Exact impedance value Exact electrical length of the lines Z01 Z02 td The impedance and time delay values are directly available once an impedance profile has been computed. Note that the impedance profile eliminates any confusion in the impedance readout. Tektronix Confidential

109
**IConnect Single-ended TDR Techniques Via L and C**

Inductance and capacitance of a via, for example, can be computed from the impedance profile using these equations. Tektronix Confidential

110
**IConnect Single-ended TDR Techniques IConnect® Modeling Process**

Extract model Simulate, compare and verify Process data Measure and acquire Here is the “Measure-Model-Verify” modeling process that we advocate. Here is how it is implemented in practice. Tektronix Confidential

111
**IConnect Single-ended TDR Techniques Modeling in IConnect Software**

* Name: Automatically Generated .subckt Single port1 port2 gnd_ ****** Partition #1 c1 port1 gnd_ 456f l1 port n ****** Partition #2 t1 1 gnd_ 2 gnd_ Z0=50.8 TD=125p ………….. ****** Partition #4 t3 3 gnd_ port2 gnd_ Z0=48.2 TD=190p .ends For single line modeling, the impedance profile waveform is partitioned and appropriate circuit topologies are selected for each partition. The segments of constant impedance are evidently the transmission lines on the board, whereas the dips and peaks in the waveform are the capacitive and inductive discontinuities. On the true impedance profile waveform, the board designer can zoom in on the part of the DUT that needs to be modeled, without running the risk of having multiple reflection effects distort the impedance of the DUT in that section of the trace. Unessential information, such as reflections at the connector-to-board interface, can be windowed out during the modeling session. Once the engineer has segmented the impedance profile waveform, TDA Systems’ IConnect® software automatically computes the impedances and propagation delays for the lines on the board and values for capacitive and inductive discontinuities. Tektronix Confidential

112
**IConnect Single-ended TDR Techniques Prepare to Simulate and Validate**

The model can then be verified using an integrated interface to SPICE. In order to prepare the model for simulations, the extracted model is complemented with a piece-wise linear source that should accurately represent the TDR oscilloscope incident step waveform during the simulation, and the same termination as the one used during the measurement. Tektronix Confidential

113
**IConnect Single-ended TDR Techniques Simulation and Validation Results**

Once a composite circuit is simulated, the resulting simulated waveform is compared to the measured waveform to verify the accuracy of the computed board trace impedance. The comparison shown on this slide clearly shows that the simulated and measured waveforms correlate well. Tektronix Confidential

114
**IConnect Single-ended TDR Techniques Using Rise Time Filtering to Achieve Simple Models**

When doing interconnect modeling, it is important to keep in mind that we need to determine a model that is no more complex than is necessary to represent the DUT accurately at the given system rise time or analog bandwidth. In light of that, let us examine the relationship between the rise time of a TDR oscilloscope and the rise time of a DUT. A typical TDR system rise time is quite fast, on the order of 30-40ps. On the other hand, even today in the world of super fast signals on the circuit board, typical rise times rarely reach 100ps, and more often are on the order of 500ps to 1ns. With faster TDR system rise times, the DUT traces may exhibit losses that are not present under normal operating conditions for the DUT. In addition, the impedance that the lumped discontinuities present to the test signal is dependent to the highest frequency present in the test signal bandwidth, as described by equations Z = 1 / (j 2pfC) Z = j 2pfL At faster rise times, the capacitive discontinuity will present a deeper "dip", whereas an inductive discontinuity will be a present a larger "spike" in relation to the impedance of the transmission lines surrounding the discontinuity. Consequently, the impedance discontinuity DZ in the DUT will be larger for a faster rise time, which may not accurately represent the impedance value at the DUT operating rise time. At the typical TDR oscilloscope rise time of about 40 ps, the correlation between the measurement and simulation of the given model is good, but not perfect. However, once both waveforms are filtered to about 150ps equivalent rise time, the discrepancies between the model simulations and measurements become negligible. The resulting model will represent the DUT with high level of accuracy at a rise time of 150ps or less. Therefore, we can conclude that using rise time filtering to verify the PCB trace model at a realistic device rise time will allow the engineer to characterize the DUT with a model that is simple, but adequate to represent the DUT accurately. Tektronix Confidential

115
**Differential transmission lines **

IConnect Differential TDR Techniques Coupled Transmission Line Modeling Is For: Differential transmission lines Differential connectors and packages that are electrically long (longer than Trise) Crosstalk prediction (differential and single ended, forward, backward) Crosstalk induced jitter prediction Tektronix Confidential

116
**IConnect Differential TDR Techniques Differential Line Modeling**

Short interconnect Use lumped-coupled model Long interconnect Split lines in multiple segments Longer yet interconnect Symmetric distributed coupled line model For longer lines, use lossy approach instead Two coupled lines are typically represented by their self and mutual inductances per unit length, in the form of LC matrices. For SPICE-type models, however, “per unit length” parameters cannot be defined. For short structures, a simple single LC pi-type lumped coupled model can be used; for longer structures, a more sophisticated model is required. Again, the rule of short interconnect can be applied to determine whether a simple LC model described above is sufficient To summarize, there are several options for modeling differential lines, which are outlined above. Tektronix Confidential

117
**IConnect Differential TDR Techniques IConnect Differential Line Modeling**

For example, for a differential line, after the impedance profiles have been computed, the impedance profile waveforms are partitioned in the Symmetric Coupled Line modeling window. The distributed model is the most appropriate in this case, given that the electrical length of the lines approaches or exceeds 1ns. Since we have assumed that in practice there could be significant common-mode propagation on the pair, the more accurate four-line model is more appropriate. Tektronix Confidential

118
**IConnect Differential TDR Techniques Composite Model Generation**

* Name: Automatically Generated .subckt Symmetric ****** Partition #1 t Z0=49.7 TD=92.3p t Z0=49.7 TD=92.3p ****** Partition #2 l n c p l n c p c f k1 l1 l2 207m .ends When the model is saved, the equivalent SPICE circuit that describes a model depicted above is obtained. A sample listing of such circuit is given in Appendix I. Tektronix Confidential

119
**IConnect Differential TDR Techniques Model Validation in IConnect**

To verify the created model, a designer needs to create a composite model in the IConnect software. The composite model complements the extracted DUT model with the source and termination that emulate the TDR measurement source and termination. Using an integrated interface to a SPICE simulator, the designer can simulate this composite model, and based on the resulting simulation waveforms, verify the accuracy of the DUT model. Both even and odd mode stimuli must be used in simulations in order to ensure that the model accurately predicts both even and odd modes of signal propagation. One can see that with the exception of the SMA connectors, which are not part of the differential line, the model accurately predicts the signal propagation. In addition, the connectors can be modeled using lumped circuit modeling capability in the IConnect software. Tektronix Confidential

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**IConnect Differential TDR Techniques Coupled LC Computation in IConnect**

Even and odd mode analysis can also be utilized for characterization of lumped interconnect structures, even when single-ended signaling schemes are utilized. Such structures as high-speed connectors, BGA packages, high-performance ATE sockets can be easily modeled using even and odd TDR measurements and equations (5). Based on the even and odd impedance profiles, the L-C matrices for the coupled structure are easily computed. A sample SPICE circuit listing obtained from the process described here is given below. Tektronix Confidential

121
**Outline Interconnect Measurement Accuracy Issues**

Interconnect SPICE / IBIS Modeling and Model Validation Topological Modeling: L and C JEDEC computation App Note: “TDR Techniques for Characterization and Modeling of Electronic Packaging” Examples: Power Plane Analysis Backplanes and cable assemblies Tektronix Confidential

122
**IConnect Short Interconnect Modeling When is Interconnect Lumped?**

trise tprop delay Practical rule of “short” or “lumped” (RLC) interconnect This practical rule of short interconnect approximately suggests when interconnect can be treated as a simple point-to-point wire characterized only by its parasitics - L and C, and its resistance R. These parasitics will still result in some rise time degradation and delay, but it will be typically not as significant as the time delay caused by the transmission line interconnect. Such an approach is typically referred to as “RLC” or “lumped” modeling approach. trise > tprop delay• (2 or 3) Tektronix Confidential

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**Use only when short compared to Trise !!!**

IConnect Short Interconnect Modeling Short Interconnect Modeling is Used For: IC packages Connectors Sockets Vias on the board Use only when short compared to Trise !!! Tektronix Confidential

124
**IConnect Short Interconnect Modeling Single Parasitic Inductance**

Parasitic inductance can be measured as a difference between the reference ground inductance and the inductance of the DUT to this ground inductance. Tektronix Confidential

125
**IConnect Short Interconnect Modeling Single-Ended TDR: Package Lead Inductance L Measurements**

TDR waveform: TDR into package lead. Short all the leads to ground on the inside of the package. Short the leads that are not being measured to ground on the outside of the package. Short waveform: TDR into the “short”; connect the probe signal contact to ground on a conductive (metal) pad For self inductance Lself, a reference short waveform is now required, which is obtained by shorting the measurement probe signal lead to ground on a piece of conductive material, such as copper. The difference between the TDR waveform of the package trace and the reference open TDR waveform will now give us the lead inductance. Fixturing requirements limit the usability of this method of inductance measurements to packages that are easily accessible on the inside. This may be a preferred method for small packages such as TSSOP, SOIC, CSP; however, if the number of leads used for a current return path to ground is small, the inductance of the return path is extracted in addition to the lead inductance. This method can also be used for larger packages, such PGA and QFP, as long as the lumped model approximation for the package lead holds. The advantage of this method is that the technique is simple, well understood and standardized. The disadvantages for package inductance measurement are obvious. There is also great possibility of not taking into account coupling of energy into leads adjacent to the lead under test. We found it to be pretty good for large packages (PGA, QFP) which had fairly high inductances and lots of faraway leads to use for a return path. However, for small packages with few extra leads, the inductance of the return path can hide that of the lead. For all types of packages, we considered the differential method to be more accurate. Induced waveform: Measure near end crosstalk with far end of the victim shorted Background waveform: Corrects for the noise and scope DC offset Tektronix Confidential

126
**IConnect Short Interconnect Modeling Single Parasitic Capacitance**

Similarly, parasitic capacitance can be measured as a difference between the reference capacitance of an open and the capacitance of the DUT to this open capacitance. Tektronix Confidential

127
**IConnect Short Interconnect Modeling Single-Ended TDR: Package Lead Capacitance C Measurements**

TDR waveform: TDR into package lead Short the leads that are not being measured to ground on the outside of the package Open waveform: TDR into the “open”;disconnect the probe from the DUT or remove the DUT from the fixture For self-capacitance Cself, a reference open waveform is required, which is obtained by disconnecting the measurement probe from the package lead, and capturing a TDR waveform while the probe is in the air. The difference between the TDR waveform of the package trace and the reference open TDR waveform gives the lead capacitance. For practical purposes, it is not necessary to integrate to infinity, but only until the difference between the Wopen and WTDR is negligibly small. For mutual capacitance Cmutual, the measurement setup is the same, but the near-end crosstalk waveform on the victim lead under test is acquired instead, while the TDR signal is sent on the offender line. Additionally, it is recommended to acquire a background noise waveform, acquired with no TDR stimulus on either of the lines, which allows us to correct for possible DC offset in TDR oscilloscope, as well as take into account any additional sources inducing a signal on the victim line. For inductance measurement, the outside leads of the package are also shorted to ground or terminated to 50 Ohms, except for the leads under test and several adjacent leads which share mutual inductance with the lead under test. On the inside of the package, however, for inductance measurement the leads must be shorted to ground. At the very least, for inductance measurement the leads must be shorted together on the inside of the package to provide a low inductance exit path for the current. Induced waveform: Measure near end crosstalk with far end of the victim open-ended Background waveform: Corrects for the noise and scope DC offset Tektronix Confidential

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**IConnect Short Interconnect Modeling Input Die Capacitance Measurement**

For self-capacitance Cself, a reference open waveform is required, which is obtained by disconnecting the measurement probe from the package lead, and capturing a TDR waveform while the probe is in the air. The difference between the TDR waveform of the package trace and the reference open TDR waveform gives the lead capacitance. For practical purposes, it is not necessary to integrate to infinity, but only until the difference between the Wopen and WTDR is negligibly small. For mutual capacitance Cmutual, the measurement setup is the same, but the near-end crosstalk waveform on the victim lead under test is acquired instead, while the TDR signal is sent on the offender line. Additionally, it is recommended to acquire a background noise waveform, acquired with no TDR stimulus on either of the lines, which allows us to correct for possible DC offset in TDR oscilloscope, as well as take into account any additional sources inducing a signal on the victim line. For inductance measurement, the outside leads of the package are also shorted to ground or terminated to 50 Ohms, except for the leads under test and several adjacent leads which share mutual inductance with the lead under test. On the inside of the package, however, for inductance measurement the leads must be shorted to ground. At the very least, for inductance measurement the leads must be shorted together on the inside of the package to provide a low inductance exit path for the current. Tektronix Confidential

129
**Compute C and L in even and odd mode**

IConnect Short Interconnect Modeling Even-Odd Mode L and C Measurements Compute C and L in even and odd mode The even and odd impedance profile analysis is useful when a coupled line model is necessary for packages and modules with complex layout, or for packages with traces that are long electrically (PGA). It has the advantages of the single-ended impedance profile analysis, but also takes into account coupling between leads under test. The even and odd impedance profile analysis allows the designer to obtain a distributed model for these complex or electrically long packages, using a methodology for differential line characterization discussed below, or to compute a complete LC matrix for a short package lead pair. However, this approach can be used only if the package lead pair in question exhibits a reasonable level of symmetry – otherwise the basic differential modeling assumption does not hold. One advantage that this approach gives the designer is that many times one can get away with a much simpler fixturing setup than otherwise required by single ended modeling techniques. For example, no shorting of the package leads on the inside of the package is required; however, good grounding on the side of the package where the stimulus is applied is still necessary for a good common mode measurement. An additional important advantage of this method compared to a single-ended method is in the more controlled field interaction in the case of area array packages, and, therefore, better measurement accuracy. For a differential measurement, a virtual ground plane created between the two leads, pads, or balls under test results in a very controlled field interaction just between these two leads, pads or balls. In case of a single-ended measurement, however, unless the leads, pads or balls are adjacent to the test leads are grounded, the interaction to these leads can change the computed inductance / capacitance values. This approach, however, may not be quite as accurate if a simple value lumped model must be extracted, and the extracted model must always be validated with a simulation from IConnect software. Tektronix Confidential

130
**IConnect Short Interconnect Modeling Even-Odd Mode Impedance Profile**

Compute C and L from even and odd Z-line Ctotal = Cself + Cm The even and odd impedance profile analysis is useful when a coupled line model is necessary for packages and modules with complex layout, or for packages with traces that are long electrically (PGA). It has the advantages of the single-ended impedance profile analysis, but also takes into account coupling between leads under test. The even and odd impedance profile analysis allows the designer to obtain a distributed model for these complex or electrically long packages, using a methodology for differential line characterization discussed below, or to compute a complete LC matrix for a short package lead pair. However, this approach can be used only if the package lead pair in question exhibits a reasonable level of symmetry – otherwise the basic differential modeling assumption does not hold. One advantage that this approach gives the designer is that many times one can get away with a much simpler fixturing setup than otherwise required by single ended modeling techniques. For example, no shorting of the package leads on the inside of the package is required; however, good grounding on the side of the package where the stimulus is applied is still necessary for a good common mode measurement. An additional important advantage of this method compared to a single-ended method is in the more controlled field interaction in the case of area array packages, and, therefore, better measurement accuracy. For a differential measurement, a virtual ground plane created between the two leads, pads, or balls under test results in a very controlled field interaction just between these two leads, pads or balls. In case of a single-ended measurement, however, unless the leads, pads or balls are adjacent to the test leads are grounded, the interaction to these leads can change the computed inductance / capacitance values. This approach, however, may not be quite as accurate if a simple value lumped model must be extracted, and the extracted model must always be validated with a simulation from IConnect software. Tektronix Confidential

131
**Outline Interconnect Measurement Accuracy Issues**

Interconnect SPICE / IBIS Modeling and Model Validation Examples: Power Plane Analysis Backplanes and cable assemblies Tektronix Confidential

132
**Power Plane Analysis Power Distribution Network (PDN) Test Vehicle**

We will use the following test structure as an example. This test board consists of two planes, which have via connections to the bottom plane, and pad connections to the top plane at multiple locations on the board. Using these vias and pads, we can apply a TDR signal across the two planes at one point (the point of power application), and measure the response across these same planes at another point (the point of power delivery). Tektronix Confidential

133
**Power Plane Analysis PDN Equivalent Models**

The series RLC model can be applied to parallel plate plane pairs, from DC to the first parallel resonance, as well as to many bypass capacitors. The parallel RLC model can be applied to shorted plane pairs, and to capacitors mounted on plane pairs around their resonance. Tektronix Confidential

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**Power Plane Analysis PDN Capacitance Measurements**

Tektronix Confidential

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**Power Plane Analysis PDN Impedance**

Tektronix Confidential

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**Power Plane Analysis PDN Resonance: Analysis for Bypass Caps**

Tektronix Confidential

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**Power Plane Analysis PDN Model Validation**

Tektronix Confidential

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**Power Plane Analysis PDN Model Accuracy**

Tektronix Confidential

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**Power Plane Via Power Via Inductance**

Tektronix Confidential

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**Power Plane Via Example: Via Modeling**

Correlation between simulation and measurement ***** Partition #1 l1 port n l2 port n k1 l1 l2 200m Tektronix Confidential

141
**Outline Interconnect Measurement Accuracy Issues**

Interconnect SPICE / IBIS Modeling and Model Validation Examples: Backplanes and cable assemblies Tektronix Confidential

142
**Putting It All Together Complete Topological Modeling Methodology**

Connectors, packages: Short structures => use lumped elements (LC) or lossless T-lines Use the true impedance profile approach Cables – lossy transmission line Backplane traces – lossy transmission line Combine the model and verify the accuracy with simulations Note that MeasureXtractor™ can do any of that! (behaviorally) Tektronix Confidential

143
**Single-ended Example Example: IConnect-Extracted Model**

W-line L=198nH, C=69.7pF Ro=0.18 Ohm Rs=0.2uOhm Gd=6.7nS (nMho) (long => lossy) LC L=700pH C=280fF T-line Z=53 Ohm Td=520ps (short => lossless) CLC L=6nH C=1.5pF Tektronix Confidential

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**Single-ended Example Simulation Results**

Tektronix Confidential

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**Differential Example Backplane Example**

Courtesy FCI Electronics Tektronix Confidential

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**Differential Example Backplane Example: PCI-X Eye Diagram**

Tektronix Confidential

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**Differential Example Backplane Example**

Differential measurement, full mode analysis Backplane Daughter Card Daughter Card Connector Connector Tektronix Confidential

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**Differential Example Daughter Card and Backplane Models**

Daughter Card Model (odd mode) Backplane Model (odd mode) Tektronix Confidential

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**Differential Example Full Daughter Card Modeling**

Tektronix Confidential

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**Differential Example Full Backplane Modeling**

Tektronix Confidential

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**Differential Example Simulation Results**

Tektronix Confidential

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**Differential Example Jitter De-Embedding: Daughter Card Only**

Tektronix Confidential

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**Differential Example Jitter De-Embedding: Backplane Only**

Tektronix Confidential

154
**Outline Interconnect Measurement Accuracy Issues**

Impedance, S-parameters and eye diagram measurements Interconnect SPICE / IBIS Modeling and Model Validation Z-line, lossy line, and automatic behavioral modeling Tektronix Confidential

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**Visit Us at the Tektronix Booth**

Tektronix Confidential

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