Presentation is loading. Please wait.

Presentation is loading. Please wait.

The NA60 Experiment Readout Architecture M.Floris, D.Marras, G.Usai, A.David, P.Rosinsky, H.Ohnishi for the NA60 Collaboration 13 th IEEE- NPSS Real Time.

Similar presentations


Presentation on theme: "The NA60 Experiment Readout Architecture M.Floris, D.Marras, G.Usai, A.David, P.Rosinsky, H.Ohnishi for the NA60 Collaboration 13 th IEEE- NPSS Real Time."— Presentation transcript:

1 The NA60 Experiment Readout Architecture M.Floris, D.Marras, G.Usai, A.David, P.Rosinsky, H.Ohnishi for the NA60 Collaboration 13 th IEEE- NPSS Real Time Conference 2003, Hotel Omni Mont Royal, Montreal, Canada, May 18 –

2 May th IEEE-NPSS Real Time Conference The NA60 Experiment Fixed target experiment at CERN SPS Heavy Ion / Dimuon experiment Open charm and prompt dimuon production Talk Outline: Apparatus DAQ Architecture Readout Electronics Conclusions NA60 SPS LEP/LHC

3 May th IEEE-NPSS Real Time Conference Detector Concept and Layout 4 Detectors: Muon Spectrometer (MWPCs, Trigger hodoscopes) ZDC Beam Tracker Vertex Detector Tracking MWPCs Trigger hodoscopes Toroidal Magnet Fe wall Muon filter ZDC and Quartz Blade TARGET AREA MUON SPECTROMETER ~1m MUON FILTER BEAM TRACKER TARGET BOX TELESCOPE Dipole field 2.5 T BEAM IC

4 May th IEEE-NPSS Real Time Conference DAQ Overview Detecto r LDC GDC Castor/ CDR burst interburst burst events - trigger DATE ALICE System is organized in indipendent partitions

5 May th IEEE-NPSS Real Time Conference PCI System Many partitions A General-purpose PCI card Many detector-specific mezzanines

6 May th IEEE-NPSS Real Time Conference Readout Chain Overview MEZZANINE 1 MEZZANINE 2 MEZZANINE 3 MEZZANINE 4 PCI Card LDC PCI BUS Acquisition software (DATE) DET.1 DET.2 DET.3 DET.4 BURST INTERBURST

7 May th IEEE-NPSS Real Time Conference Hardware/Software Handshake #0#1#2# Acquisition Software 00: idle 10: burst 11: interburst bits 0-1: SPS status bit 2: R/O status bit3: timeout timeout At the end of the burst HW sets bit 2 SW starts as soon as bit 2 is set and resets it at the end If a new burst arrives while SW is still reading bit 3 is set BURST

8 May th IEEE-NPSS Real Time Conference PCI Card Architecture PCI interface application RAM Registers Control logic mez. PCI CTRL BURST INTERBURST det. PCI Card FPGA Large memory buffer Mezzanine Cards Registers Light blue: blocks inside FPGA

9 May th IEEE-NPSS Real Time Conference First Implementation – PCI-FLIC Developed by EP/ED-DTb CERN Division PCI core embedded in ORCA FPGA Successfully used in test beams in 2001/2002 Readout architecture validated Has some limitations Slow FPGA Maintenance problems A new card has been developed...

10 May th IEEE-NPSS Real Time Conference Final Implementation – PCI-CFD New and faster ALTERA FPGA External PCI bridge (PLX 9030) X4 bandwidth FPGA (APEX/ 20K100) PLX9030 PCI bridge PMC connectors for mezzanine cards 64 MBytes RAM Will be used in next NA60 run

11 May th IEEE-NPSS Real Time Conference CFD – FPGA Application Readout Event Formatting RAM Writing PCI Interface BURST INTER BURST # total words (8bit) readout time # total words (8bit) # event# burst time of arrival data 5 data 3 data 1 data 4 data 2 data N - 2data N - 1 data N marker word # data words (8bit) errors Data Header Trailer 31 0

12 May th IEEE-NPSS Real Time Conference Mezzanine 1 – VME-Like & CAMAC Protocols Very simple mezzanine Level conversion ECL/NIM => TTL Protocol itself implemented in PCI Card FPGA BURST WARNING TRIGGER BUSY Protocol control signals & data PCI Card

13 May th IEEE-NPSS Real Time Conference Mezzanine 1 – Protocols 2 different protocols implemented on this mezzanine: RMH Protocol (Muon Spectrometer MWPCs & Hodoscopes) Fera (CAMAC) protocol (Beam Tracker & ZDC) trigger start_read encode dflag data end_of_read RMH Protocol

14 May th IEEE-NPSS Real Time Conference Mezzanine 2 - Pixel Detector Alice PILOT chip, radhard, Pixel chip configuration and readout, GOL interfacing ALICE1LHCb Pixel chip, radhard, 256x32 cells (425 m x 50 m) GOL, radhard high speed serial link (GLink) GOL (Pix DATA) Pixel/PILOT (JTAG Conf.) thanks… alice

15 May th IEEE-NPSS Real Time Conference Mezzanine 2 – Mezzanine Features Complex mezzanine Can be interfaced to 2 pixel planes R/O implemented in local FPGA Zero Suppression Event formatting Error detection PCI accesses FIFOs Detector configuration

16 May th IEEE-NPSS Real Time Conference Mezzanine 2 – Pixel Conf&Test Software Mezzanine & pixel- chip configuration (JTAG) Settings database Detector & R/O Chip test Threshold scan Noisy and dead pixel Used by DATE at run startup

17 May th IEEE-NPSS Real Time Conference Conclusions A new readout system based on the PCI bus has been developed for a HEP experiment High performances and flexibility, low costs Roadmap: Muon spectrometer electronics commissioned October 2001 Beam Tracker and ZDC electronics used for the first time June 2002 Pixel Telescope intermediate system working on beam June & October 2002 Final system working in lab, will be used in data taking August 2003

18 May th IEEE-NPSS Real Time Conference Acknowledgements The authors would like to thank the following people: CERN EP/ED-DTb group and in particular Hans Muller for their contributions and suggestions in the early stages of the project The Alice Pixel group and in particular F.Formenti, G.Stefanini, K.Wyllie, A.Kluge and M.Burns for their constant support to the NA60 pixel project

19 May th IEEE-NPSS Real Time Conference NA60 Collaboration 50 people, 12 institutes, 7 countries Lisbon CERN Bern Torino Yerevan Cagliari Lyon Clermont BNL Riken Stony Brook Palaiseau R. Arnaldi, K. Banicz, K. Borer, J. Buytaert, J. Castor, B. Chaurand, W. Chen, B. Cheynis, C. Cicalò, A. Colla, P. Cortese, A. David, A. de Falco, N. de Marco, A. Devaux, A. Devismes, A. Drees, L. Ducroux, H. Enyo, A. Ferretti, M. Floris, P. Force, A. Grigorian, J.Y. Grossiord, N. Guettet, A. Guichard, H. Gulkanian, J. Heuser, M. Keil, L. Kluberg, Z. Li, C. Lourenço, J. Lozano, F. Manso, A. Masoni, A. Neves, H. Ohnishi, C. Oppedisano, G. Puddu, E. Radermacher, P. Rosinský, E. Scomparin, J. Seixas, S. Serci, R. Shahoyan, E. Siddi, P. Sonderegger, G. Usai, H. Vardanyan and H. Wöhri


Download ppt "The NA60 Experiment Readout Architecture M.Floris, D.Marras, G.Usai, A.David, P.Rosinsky, H.Ohnishi for the NA60 Collaboration 13 th IEEE- NPSS Real Time."

Similar presentations


Ads by Google