4. One physical processor – may consist of one or more cores One processing unit – may consist of one or more logical processors One logical computing engine in the OS, application and driver view Non-Uniform Memory Architecture Group of logical processors, cache and memory that are in proximity to each other I/O is an optional part of a NUMA Node Logical grouping of up to 64 logical processors

5. 128 Logical Processor System Group (up to 64 logical processors) Group (up to 64 logical processors) NUMA Node Socket Core Logical Processor

7. 1.7X 128LP 64LP

12. 30 HP SmartArray P600 HBAs (x4 3Gb SAS) 60 HP MSA70 Disk Arrays 1440 72GB 2.5” 15Krpm Disks A 64-core configuration can achieve 200,000 IOps for 8-64 KB requests 64 dual-core hyper-threaded “Montvale” 9100 1.6 GHz Itanium2 w/ 24 GB LLC 1 TB Memory, 4 dual-port 1GB NICs

13. 32 dual-core hyper-threaded “Tulsa” 7100 3.4 GHz Xeon w/ 16 GB LLC 24 Emulex LP10002 dual-port FC HBAs 48 HP MSA1000/1500 Disk Arrays 1540 36GB 3.5” 15Krpm Disks 256 GB Memory

16. New Structures Group relative processor affinity and processor number typedef struct _GROUP_AFFINITY { KAFFINITY Mask; USHORT Group; USHORT Reserved[3]; } GROUP_AFFINITY, *PGROUP_AFFINITY; typedef struct _PROCESSOR_NUMBER { USHORT Group; UCHAR Number; UCHAR Reserved; } PROCESSOR_NUMBER, *PPROCESSOR_NUMBER;

19. GetActiveProcessorGroup Count Returns the number of active groups in the system GetMaximumProcessor GroupCount Returns the maximum number of groups that the system supports GetActiveProcessorCount Returns the number of active LPs in a group or in the system GetMaximumProcessor Count Returns the maximum number of LPs that a group or the system can support GetThreadGroupAffinity Returns the current group affinity of the thread (in GROUP_AFFINITY) SetThreadGroupAffinity Sets the affinity of the thread to a set of LPs within a specified group (in GROUP_AFFINITY) CreateRemoteThreadEx Enables an application to change the default thread group affinity and specify an ideal LP for a thread GetNumaNodeNumber FromHandle Returns the node number associated with a handle (e.g. file and socket handles)

22. P1P1 Cache 1 Mem A Node Interconnect Mem B Disk A P3P3 Cache 3 P4P4 Cache 4 Cache(s) (0) (3) (4) (1) (7) I/O InitiatorI/O InitiatorISR I/O Buffer Home DPC (2)(6) (5) P2P2 Cache 2 Disk B Locked out for I/O Initiation outLocked out for I/O Initiation

23. P1P1 Cache 1 Mem A Node Interconnect Mem B Disk A P3P3 Cache 3 P4P4 Cache 4 Cache(s) (3) I/O Initiator ISRDPC (2) P2P2 Cache 2 Disk B ISR (2)

26. All dates, product features and plans are subject to change without notice. Intel ® Xeon ® MP 7000 Sequence (Expandable, MC) Intel ® Xeon ® DP 5000 Sequence (Efficient Performance) Intel ® Xeon ® UP 3000 Sequence (Entry) Intel ® Xeon ® WS 5000 Sequence (Workstation & HPC) Intel ® Itanium ® 9000 Sequence (Mission Critical) Future2008 Nehalem Processor Future EX Chipset Nehalem Processor Future EX Chipset Itanium Processor 870 / OEM Chipset Itanium Processor 870 / OEM Chipset Future MC Chipset Kittson Nehalem Processor Future EN Chipset Nehalem Processor Future EN Chipset Quad/Dual-core Xeon Processor Intel® 3200 Chipset Quad/Dual-core Xeon Processor Intel® 3200 Chipset Quad/Dual-core Xeon Processor Intel® 7300 Chipset Quad/Dual-core Xeon Processor Intel® 7300 Chipset Quad/Dual-core Xeon Processor Intel® 5100 Chipset Quad/Dual-core Xeon Processor Intel® 5100 Chipset Nehalem Processor Future EP Chipset Nehalem Processor Future EP Chipset Quad/Dual-core Xeon Processor Intel® 5000 Chipset Quad/Dual-core Xeon Processor Intel® 5000 Chipset Nehalem Processor Future EP Chipset Nehalem Processor Future EP Chipset Quad/Dual-core Xeon Processor Intel® 5400 Chipset Quad/Dual-core Xeon Processor Intel® 5400 Chipset Nehalem Processor Future WS Chipset Nehalem Processor Future WS Chipset Dunnington Poulson Tukwila

27. PCI Express* I/OHub ICH DMI DMI Nehalem PCIExpress*PCIExpress* 2, 4, 8 Cores per socket, two logical processors per core Expect large Nehalem-EX systems with 128-256 logical processors Intel® QuickPath Architecture Integrated Memory Controller Buffered or Un-buffered Memory *Optional Integrated Graphics Intel QuickPath Interconnect Nehalem I/OHub I/OHub

28. Nehalem-EX Nehalem-EPHavendale Expandable (4S+) Efficient Performance (2S) High End Desktop Mainstream Client Thin and Light Notebook Server and Workstation Auburndale Clarksfield Lynnfield Business and Consumer Clients

29. Number Of Processors Increasing Straining Interrupt addressability limits

30. Interrupt Addressing xAPIC has been meeting interrupt architecture needs since P4, for Intel Architecture 8 bit APIC ID addresses Physical addresses limited to 0 – 254 APIC IDs Logical addresses limited to 60 processors Flat addresses limited to 8 processors Nehalem processors require 16 APIC IDs per socket for 8 processors Interrupt addressing strained on Nehalem platforms xAPIC can address only up to 8 socket Nehalem Only 128 processors Next Generation Interrupt Architecture allows scaling to 256 processors on Nehalem platforms

34. Core 2 Thread 3 Thread 3 Non-running threads Core 1 Thread 4 Thread 4 Thread 5 Thread 5 Thread 1 Thread 1 Thread 2 Thread 2 Thread 6 Thread 6 Core 2 Core 1 User Thread 2 User Thread 2 Kernel Thread 2 Kernel Thread 2 User Thread 1 User Thread 1 Kernel Thread 1 Kernel Thread 1 User Thread 3 User Thread 3 Kernel Thread 3 Kernel Thread 3 User Thread 4 User Thread 4 Kernel Thread 4 Kernel Thread 4 User Thread 5 User Thread 5 Kernel Thread 5 Kernel Thread 5 User Thread 6 User Thread 6 Kernel Thread 6 Kernel Thread 6

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38. © 2008 Microsoft Corporation. All rights reserved. Microsoft, Windows, Windows Vista and other product names are or may be registered trademarks and/or trademarks in the U.S. and/or other countries. The information herein is for informational purposes only and represents the current view of Microsoft Corporation as of the date of this presentation. Because Microsoft must respond to changing market conditions, it should not be interpreted to be a commitment on the part of Microsoft, and Microsoft cannot guarantee the accuracy of any information provided after the date of this presentation. MICROSOFT MAKES NO WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, AS TO THE INFORMATION IN THIS PRESENTATION.