Presentation on theme: "Processor Organization and Architecture"— Presentation transcript:
1 Processor Organization and Architecture Module IIIProcessor Organization and Architecture
2 Nano-programmingIn this method, microinstructions does not generate control signals directly but uses a second control memory called Nano Control Memory (NCM)There are two levels of control memory:higher level Micro Control Memory &lower level NCM that stores nano-instructions
4 Nano-programmingSuppose there are n = 2048 micro-ops each of 41 bits wide,The memory required for single control ROM is 2048 x 41 =83,968 bits
5 Nano-programming Suppose there are 100 unique control words in ROM. These 100 words can be uniquely saved in nano control ROM saving space as shown:
6 Nano-programming Advantage: Disadvantage: Reduces total size of required control memoryGreater design flexibilityDisadvantage:Less speed due to two level memory
7 Classification based on instruction sets Complex Instruction Set ComputersReduced Instruction Set Computers
8 Complex Instruction Set Computers CISC processor mostly uses a unified cache for both data and instructions and shares the same pathThey mostly use microprogrammed CU and hence control memory is required and it slows down the execution
10 CISC CharacteristicsIt tries to simplify the compilation and improve the overall computer performance.CISC architecture attempt to provide a single machine instruction for every statement in a high-level language.It incorporates variable-length instruction formats.Packing variable instruction formats in memory requires special decoding circuits.
11 CISC Characteristics Instructions manipulate operands in memory Uses a variety of addressing modes—from 5 to 20Uses a large number of instructions—from 100 to 250Includes specialized instructions which are used infrequentlyExamples : Motorola family, Intel x86 CPUs-Pentium
12 Reduced Instruction Set Computers It uses separate instruction and data caches and their access paths are differentIt uses hardwired control unit and hence faster execution.
14 RISC CharacteristicsUses a small set of instructions with register-to-register operations and simple load and store operations for memory.Uses only a few addressing modesFollows a simple instruction formatinstruction length is fixed and aligned on word boundaries.Instructions are easy to decode.Hardwired control makes faster execution
15 RISC Characteristics Execute one instruction per clock cycle Includes pipeliningLoad or store may require two clock cycles.Uses a large number of registersoverlapped register windows speed-up procedure call and return.Thus register-to-memory operations is minimizedExamples : SPARC, Alpha,...
16 RISC vs CISC RISC CISC Contains simple instructions of one clock cycle Very few instructions refer to memoryHardwired Control UnitFixed Format InstructionsContains complex instructions taking more than one clock cycleMost of the instructions may refer memoryMicro-programmed Control UnitVariable Format Instructions
17 RISC vs CISC RISC CISC Few Instructions Few Addressing Modes Many RegistersComplexity is in compilerFaster clock ratesReduces the cycles per instruction at the cost of the number of instructions per program.Many InstructionsMany Addressing ModesFew RegistersComplexity is in microprogramSlower clock ratesMinimize the number of instructions per program sacrificing the number of cycles per instruction.