1. 1. Introduction 2. Methods for I/O Operations 3. Buses 4. Liquid Crystal Displays 5. Other Types of Displays 6. Graphics Adapters 7. Optical Discs 12/11/20141Input/Output Systems and Peripheral Devices (06-1)

2. Structure of a Graphics Adapter Color Representation Video Memory Graphics Accelerators 3D Accelerators Graphics Processing Units Digital Interfaces for Monitors 12/11/20142Input/Output Systems and Peripheral Devices (06-1)

3. 12/11/20143Input/Output Systems and Peripheral Devices (06-1)

4. Graphics Controller Implements the main functions of the graphics adapter System Bus Interface Transfers in burst mode Transfers with no wait states when reading the video memory FIFO memory for efficient write to the video memory 12/11/20144Input/Output Systems and Peripheral Devices (06-1)

5. Video Memory Interface Allows to update the video images VGA Registers and Control Registers Enable programming of the video adapter for operation in VGA modes There are adapters that are no longer compatible with the VGA standard Cursor Generator Graphic Functions Implemented by graphics accelerators 12/11/20145Input/Output Systems and Peripheral Devices (06-1)

6. Video BIOS Provides video functions for access to the graphics adapter The BIOS programs of different adapters are different  difficult programming VESA (Video Electronics Standards Association) standard for high-resolution BIOS functions Video Memory Holds the video image  frame buffer 12/11/20146Input/Output Systems and Peripheral Devices (06-1)

7. RAMDAC Circuit (RAMDAC – RAM Digital to Analog Converter) Reads the digital image and converts it into analog signals The RAMDAC functions may be integrated into the graphics controller Only required for displays with analog inputs Displays that operate in the digital domain reconvert the analog signals to digital form 12/11/20147Input/Output Systems and Peripheral Devices (06-1)

8. CRT Controller (CRT – Cathode Ray Tube) Generates the synchronization signals required for displaying the images by a CRT monitor: S H, S V Clock Generator Converts the quartz oscillator frequency to the frequencies needed for the graphics controller, CRT controller, and RAMDAC circuit 12/11/20148Input/Output Systems and Peripheral Devices (06-1)

9. Video Ports Enable to transfer the video images to a monitor There are several variants of video ports VGA (Video Graphics Array) Analog interface Designed for CRT displays, but also used by some liquid crystal displays Electrical noise may occur DB-15 connector 12/11/20149Input/Output Systems and Peripheral Devices (06-1)

10. VIVO (Video In Video Out) Analog interface for connecting to TV sets, DVD players, game consoles (TV Out) Signals: S-Video (Y/C); composite video; component video (e.g., RGB) 9-pin mini-DIN connector DVI (Digital Visual Interface) Digital interface DVI-I (digital and analog signals) or DVI-D (digital signals only) connector 12/11/201410Input/Output Systems and Peripheral Devices (06-1)

11. Video adapter with VGA, VIVO, and DVI ports 12/11/2014 Input/Output Systems and Peripheral Devices (06-1) 11

12. HDMI (High-Definition Multimedia Interface) Digital interface for uncompressed video data Allows to send digital audio data over the same cable 19-pin (single-link) or 29-pin (dual-link) connector DisplayPort Digital interface for video and audio data Targeted to replace the VGA and DVI interfaces 20-pin connectors for 1, 2, or 4 lanes 12/11/201412Input/Output Systems and Peripheral Devices (06-1)

13. Structure of a Graphics Adapter Color Representation Video Memory Graphics Accelerators 3D Accelerators Graphics Processing Units Digital Interfaces for Monitors 12/11/201413Input/Output Systems and Peripheral Devices (06-1)

14. (a) 8 bits to represent a pixel color Pseudo-color mode 256 colors A RAM CLUT (Color Look-Up Table) is used to extend the number of colors 12/11/201414Input/Output Systems and Peripheral Devices (06-1)

15. (b) 15 bits for each pixel 32,768 colors In the video memory, 16 bits are allocated for each pixel 5 bits for each primary color 12/11/201415Input/Output Systems and Peripheral Devices (06-1)

16. (c) 16 bits for each pixel 65,536 colors 6 bits are allocated for the green color 5 bits are allocated for each of the red and blue colors High Color mode 12/11/201416Input/Output Systems and Peripheral Devices (06-1)

17. (d) 32 bits for each pixel The 8 MSBs are not used 16,777,216 colors Un-compacted pixel mode Allows to simplify the adapter structure Reduces the efficiency of memory use 12/11/201417Input/Output Systems and Peripheral Devices (06-1)

18. (e) 24 bits for each pixel 16,777,216 colors Compacted pixel mode The video memory is used more efficiently Reduces the required transfer rate (d), (e): True Color modes 12/11/201418Input/Output Systems and Peripheral Devices (06-1)

19. Structure of a Graphics Adapter Color Representation Video Memory Graphics Accelerators 3D Accelerators Graphics Processing Units Digital Interfaces for Monitors 12/11/201419Input/Output Systems and Peripheral Devices (06-1)

20. Video memories can be single-ported or dual-ported Single-ported video memory The unique data port is used to refresh the screen and to write new data by the CPU or graphics controller The operations cannot be performed in parallel The transfer rate must be enough for all these operations 12/11/201420Input/Output Systems and Peripheral Devices (06-1)

21. Placement of a single-ported video memory 12/11/2014 Input/Output Systems and Peripheral Devices (06-1) 21

22. Dual-ported video memory One of the ports is used to update the images in memory The second port has serial access and is used to refresh the images on the screen Memory update and screen refresh can be performed in parallel An external RAMDAC circuit is needed 12/11/201422Input/Output Systems and Peripheral Devices (06-1)

23. Placement of a dual-ported video memory 12/11/2014 Input/Output Systems and Peripheral Devices (06-1) 23

24. Video Memory Size Determines the maximum resolution and number of colors that can be displayed The required memory size is: S = (R X  R Y  Bpp) / 8 R X, R Y – no. of pixels horizontally/vertically Bpp – no. of color bits per pixel A larger video memory is required  3D accelerators 12/11/201424Input/Output Systems and Peripheral Devices (06-1)

25. Video Memory Transfer Rate The maximum transfer rate  bandwidth Affected by video memory technology and access time Bandwidth has to be shared by: screen refreshing circuits, CPU, graphics controller 30.. 50% of the bandwidth should be reserved for other functions, different than refreshing 12/11/201425Input/Output Systems and Peripheral Devices (06-1)

26. DDR-400 (PC3200) memory Maximum transfer rate: 3,200 MB/s Average transfer rate: ~1,600 MB/s DDR2-667 (PC2-5300) memory Maximum transfer rate : 5.336 GB/s DDR3-1600 (PC3-12800) memory Maximum transfer rate : 12.8 GB/s DDR4-2400 (PC4-19200) memory Maximum transfer rate : 19.2 GB/s 12/11/201426Input/Output Systems and Peripheral Devices (06-1)

27. GDDR (Graphics Double Data Rate) Designed by ATI Technologies with the collaboration of the JEDEC committee Several versions: GDDR2.. GDDR5 GDDR2 and GDDR3: based on DDR2 technology GDDR4 and GDDR5: based on DDR3 technology Low voltage: 1.8 V.. 1.5 V  reduced power consumption and heat output Separate data strobe signals for read and write 12/11/201427Input/Output Systems and Peripheral Devices (06-1)

28. GDDR5 Combines high performance with stable operation and low implementation costs Memory organization:  32 Differential command clock signal (CK, CK#) Two diff. write clock signals (WCK, WCK#) Two data bytes are aligned to one WCK signal Example for a data rate of 5 Gbits/s: f CK = 1.25 GHz; f WCK = 2.5 GHz 12/11/201428Input/Output Systems and Peripheral Devices (06-1)

29. Data bus inversion Reduces the number of zero bits transmitted Indicated with a DBI# signal for each byte Transmission lines have high level termination  power dissipation is reduced Address bus inversion Signal training Phase adjustment of clock, data, and address signals 12/11/201429Input/Output Systems and Peripheral Devices (06-1)

30. Address training: alignment of the address bus to the CK clock signal Alignment of WCK signal to the CK signal Data training: alignment of the data lines to the corresponding WCK signal A “hidden” data re-training is possible Calibration: improves the reliability Auto-calibration: drive strength, termination impedance Software-controlled adjustment 12/11/201430Input/Output Systems and Peripheral Devices (06-1)

31. Burst read/write access to the internal memory: 8 bits/pin  256 bits (two CK cycles) Maximum transfer rates of 4.. 7 Gbits/s per pin  16.. 28 GB/s for 32 pins Error detection Dedicated EDC (Error Detection Code) pins for sending CRC codes to the controller CRC code: for each data byte + DBI# line Allows to detect single-bit and double-bit errors 12/11/201431Input/Output Systems and Peripheral Devices (06-1)

32. Power management Features that allow to consume power only when it is needed Scalable clock frequency and data rate: 5 Gbits/s.. 200 Mbits/s Low power mode for the DRAM core Multiple levels for termination impedance: increasing the impedance at slower data rates Low supply voltage: 1.5 V Data and address bus inversion 12/11/201432Input/Output Systems and Peripheral Devices (06-1)

33. Structure of a Graphics Adapter Color Representation Video Memory Graphics Accelerators 3D Accelerators Graphics Processing Units Digital Interfaces for Monitors 12/11/201433Input/Output Systems and Peripheral Devices (06-1)

34. Contain specialized circuits to execute the mathematical operations required for graphics rendering Release the CPU from the task of executing these operations The first graphics accelerators: AVGA (Accelerated VGA) adapters Subsequent graphics accelerators: 2D accelerators The link between the accelerator circuitry and the OS is made via a driver 12/11/201434Input/Output Systems and Peripheral Devices (06-1)

35. Common 2D graphics functions: BitBlt (Bit Block Transfer) Two bitmaps are combined with a raster operation  Boolean operator The result is transferred to the destination area Blitter: dedicated circuit for the BitBlt operation Tracing lines, drawing rectangles, circles Filling surfaces or polygons Adding color 12/11/201435Input/Output Systems and Peripheral Devices (06-1)

36. Multimedia accelerators: graphics accelerators extended with audio and video acceleration functions Functions: Decoding audio data streams Scaling video images in x, y directions Converting digital video signals into RGB signals Decompressing video images represented in various formats 12/11/201436Input/Output Systems and Peripheral Devices (06-1)

37. Structure of a Graphics Adapter Color Representation Video Memory Graphics Accelerators 3D Accelerators Graphics Processing Units Digital Interfaces for Monitors 12/11/201437Input/Output Systems and Peripheral Devices (06-1)

38. 3D Accelerators The Need for 3D Accelerators 3D Images 3D Operations 12/11/201438Input/Output Systems and Peripheral Devices (06-1)

39. The monitor screen is two-dimensional  the images displayed must be two- dimensional To display 3D objects, they must be converted into 2D images Complex computations are needed to translate 3D images into 2D images A 3D accelerator allows the programs to display virtual 3D images with a high level of details 12/11/201439Input/Output Systems and Peripheral Devices (06-1)

40. 3D Accelerators The Need for 3D Accelerators 3D Images 3D Operations 12/11/201440Input/Output Systems and Peripheral Devices (06-1)

41. Are managed using abstract models An object is represented as a set of points defined by its x, y, and z coordinates  position of vertices If the object vertices are connected with lines, surfaces are obtained  can be filled with a certain color or texture Each 3D object is composed of a large number of triangles (or polygons) that describe its surface 12/11/201441Input/Output Systems and Peripheral Devices (06-1)

42. Animated 3D graphics requires to perform a series of geometry computations that define the position of objects in 3D space The geometry computations that handle the vertices of triangles can be performed by the CPU or by the graphics processor The graphics processor must convert these triangles into solid surfaces  intensive computations are needed 12/11/201442Input/Output Systems and Peripheral Devices (06-1)

43. In the real world, objects interact with each other Complex mathematical equations are used to determine whether an object is visible in a scene from a given angle Besides the color components, for each pixel an alpha value must also be stored Indicates the degree of transparency of the pixel in the final image 12/11/201443Input/Output Systems and Peripheral Devices (06-1)

44. Another information that must be stored: the depth in space or z coordinate The accelerator determines the z value of the objects’ pixels in a plane and displays those with a smaller z value The pixels’ depth information is stored in a separate buffer  z-buffer Usually, 32 bits are allocated in the z-buffer for each pixel 12/11/201444Input/Output Systems and Peripheral Devices (06-1)

45. Each time the image is updated, the color and depth of pixels must be recomputed Applying different 3D computations to the scene  process of rendering Fills in all of the points on the surface of the object that previously was stored only as a set of vertices A solid object with 3D effects will be drawn on the monitor 12/11/201445Input/Output Systems and Peripheral Devices (06-1)

46. 3D Accelerators The Need for 3D Accelerators 3D Images 3D Operations 12/11/201446Input/Output Systems and Peripheral Devices (06-1)

47. 3D operations are performed in two stages: Geometry stage: clipping, transformation, lighting Rendering stage: shading, texture mapping with adding the perspective effect, texture filtering, alpha blending On current 3D accelerators, operations in both stages are performed by the graphics processor 12/11/201447Input/Output Systems and Peripheral Devices (06-1)

48. 12/11/201448Input/Output Systems and Peripheral Devices (06-1)

49. Clipping Determines what part of an object is visible on the screen Transformation Translation; reflection; glide reflection; scaling Lighting Lighting effects create color shading, light reflection, shadows 12/11/201449Input/Output Systems and Peripheral Devices (06-1)

50. Tessellation Dividing polygons into smaller structures for rendering; triangles may be used Shading Enables to better define the shape of an object Texture Mapping Adding surface details (textures) to polygons that represent objects 12/11/201450Input/Output Systems and Peripheral Devices (06-1)

51. Texture Filtering The color of a new pixel is determined through interpolation between the colors of several texels in the original texture Bilinear filtering: uses the weighted average of the four texels nearest to a particular texel Trilinear filtering 3D accelerators store in memory several variants of a texture  “MIP mapping” Combining this feature with bilinear filtering 12/11/201451Input/Output Systems and Peripheral Devices (06-1)

52. Fogging Gradually fading objects in the distance Alpha Blending Used to create the transparency effect for some objects (e.g., windows) Anti-Aliasing Oblique lines: approximated by combining vertical segments with horizontal segments Removing this effect: changing the color of pixels near the outlines 12/11/201452Input/Output Systems and Peripheral Devices (06-1)

53. The main component of a graphics adapter is the graphics controller It contains the system bus interface; the speed of this interface is an important performance factor Video ports enable to combine video images from other sources with the graphics images The transfer rate of the video memory has a major impact on performance Dual-ported memories: updating the images and refreshing the screen can be performed in parallel 12/11/201453Input/Output Systems and Peripheral Devices (06-1)

54. The GDDR5 memory has advanced features for high performance and stable operation Data and address bus inversion; signal training; calibration; error detection; power management 3D accelerators are required to convert 3D objects into 2D images in a realistic manner For each pixel of a 3D object, an alpha value and the z coordinate have to be stored 3D operations are performed in two stages: geometry stage and rendering stage 12/11/201454Input/Output Systems and Peripheral Devices (06-1)

55. Structure of a graphics adapter Components of the graphics controller Function of the RAMDAC circuit Variants of video ports Un-compacted pixel mode for color representation Compacted pixel mode for color representation Single-ported video memory Dual-ported video memory 12/11/201455Input/Output Systems and Peripheral Devices (06-1)

56. Features of the GDDR5 graphics memory Data and address bus inversion of the GDDR5 graphics memory Signal training of the GDDR5 graphics memory Representation of 3D objects Stages for performing 3D operations 3D operations performed in the geometry stage 3D operations performed in the rendering stage 12/11/201456Input/Output Systems and Peripheral Devices (06-1)

57. 1.What is the advantage of a dual-ported video memory? 2.What are the power management features of the GDDR5 video memory? 3.What information is required for representing 3D objects? 4.What operations are performed in the rendering stage for 3D images? 12/11/201457Input/Output Systems and Peripheral Devices (06-1)