1. System On Chip - SoC
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7. Outline Introduction What is SoC ? SoC characteristics
Benefits and drawbacks
Solution
Major SoC Applications
Summary

8. Introduction Technological Advances
today’s chip can contains 100M transistors
transistor gate lengths are now in term of nano meters
approximately every 18 months the number of transistors on a chip doubles – Moore’s law
The Consequences
components connected on a Printed Circuit Board can now be integrated onto single chip
hence the development of System-On-Chip design

9. Outline Introduction What is SoC ? SoC characteristics
Benefits and drawbacks
Solution
Major SoC Applications
Summary

10. What is SoC ?
People A:
The VLSI manufacturing technology advances has made possible to put millions of transistors on a single die. It enables designers to put systems-on-a-chip that move everything from the board onto the chip eventually.
People B:
SoC is a high performance microprocessor, since we can program and give instruction to the uP to do whatever you want to do.
People C:
SoC is the efforts to integrate heterogeneous or different types of silicon IPs on to the same chip, like memory, uP, random logics, and analog circuitry.
All of the above are partially right, but not very accurate!!!

11. What is SoC ? SoC not only chip, but more on “system”.
SoC = Chip + Software + Integration
The SoC chip includes:
Embedded processor
ASIC Logics and analog circuitry
Embedded memory
The SoC Software includes:
OS, compiler, simulator, firmware, driver, protocol stackIntegrated development environment (debugger, linker, ICE)Application interface (C/C++, assembly)
The SoC Integration includes :
The whole system solution
Manufacture consultant
Technical Supporting

12. Outline Introduction What is SoC ? SoC characteristics
Benefits and drawbacks
Solution
Major SoC Applications
Summary

13. System on Chip architecture
ASIC Typical Design Steps
Typical ASIC design can take up to two years to complete
Top Level Design
Unit Block Design
Unit Block Verification
Integration and Synthesis
Trial Netlists
Timing Convergence
& Verification
System Level Verification
Fabrication
DVT Prep
DVT 6 12 12 4
14 ?? 5 8
Time in Weeks 48
Time to Mask order 61

14. System on Chip architecture
With increasing Complexity of IC’s and decreasing Geometry, IC Vendor steps of Placement, Layout and Fabrication are unlikely to be greatly reduced
In fact there is a greater risk that Timing Convergence steps will involve more iteration.
Need to reduce time before Vendor Steps.
Need to consider Layout issues up-front.
SoC Typical Design Steps
Top Level Design
Unit Block Design
Unit Block Verification
Integration and Synthesis
Trial Netlists
Timing Convergence
& Verification
System Level Verification
Fabrication
DVT Prep
DVT 4 4 2 14 5 4
Time in Weeks 24
Time to Mask order 33

15. System on Chip interconnection
Design reuse is facilitated if “standard” internal connection buses are used .
All cores connect to the bus via a standard interface .
Any-to-any connections easy but …
Not all connections are necessary .
Global clocking scheme .
Power consumption .
Standardization is being addressed by the Virtual Socket Interface Alliance (VSIA)

16. System on Chip interconnection
AMBA (Advanced Microcontroller Bus Architecture) is a collection of buses from ARM for satisfying a range of different criteria.
APB (Advanced Peripheral Bus): simple strobed-access bus with minimal interface complexity. Suitable for hosting peripherals.
ASB (Advanced System Bus): a multimaster synchronous system bus.
AHB (Advanced High Performance Bus): a high- throughput synchronous system backbone. Burst transfers and split transactions.

17. System on Chip cores
One solution to the design productivity gap is to make ASIC designs more standardized by reusing segments of previously manufactured chips.
These segments are known as “blocks”, “macros”, “cores” or “cells”.
The blocks can either be developed in-house or licensed from an IP company.
Cores are the basic building blocks .

18. System on Chip cores Soft Macro Firm Macro Hard Macro
Reusable synthesizable RTL or netlist of generic library elements
User of the core is responsible for the implementation and layout
Firm Macro
Structurally and topologically optimized for performance and area through floor planning and placement
Exist as synthesized code or as a netlist of generic library elements
Hard Macro
Reusable blocks optimized for performance, power, size and mapped to a specific process technology
Exist as fully placed and routed netlist and as a fixed layout such as in GDSII format .

19. System on Chip cores Soft core Firm core Hard core Reusability
portability
flexibility
Firm
core
Hard
core
Predictability, performance, time to market

20. System on Chip cores
Locating the required cores and associated contract discussions can be a lengthy process
Identification of IP vendors
Evaluation criteria
Comparative evaluation exercise
Choice of core
Contract negotiations
Reuse restrictions
Costs: license, royalty, tool costs
Core integration, simulation and verification

21. Outline Introduction What is SoC ? SoC characteristics
Benefits and drawbacks
Solution
Major SoC Applications
Summary

22. The Benefits
There are several benefits in integrating a large digital system into a single integrated circuit .
These include
Lower cost per gate .
Lower power consumption .
Faster circuit operation .
More reliable implementation .
Smaller physical size .
Greater design security .

23. The Drawbacks
The principle drawbacks of SoC design are associated with the design pressures imposed on today’s engineers , such as :
Time-to-market demands .
Exponential fabrication cost .
Increased system complexity .
Increased verification requirements .

24. Design gap

25. Outline Introduction What is SoC ? SoC characteristics
Benefits and drawbacks
Solution
Major SoC Applications
Summary

26. Solution is Design Re-use
Overcome complexity and verification issues by designing Intellectual Property (IP) to be re-usable .
Done on such a scale that a new industry has been developed.
Design activity is split into two groups:
IP Authors – producers .
IP Integrators – consumers .
IP Authors produce fully verified IP libraries
Thus making overall verification task more manageable
IP Integrators select, evaluate, integrate IP from multiple vendors
IP integrated onto Integration Platform designed with specific application in mind

27. Outline Introduction What is SoC ? SoC characteristics
Benefits and drawbacks
Solution
Major SoC Applications
Summary

28. Major SoC Applications
Speech Signal Processing .
Image and Video Signal Processing .
Information Technologies
PC interface (USB, PCI,PCI-Express, IDE,..etc) Computer peripheries (printer control, LCD monitor controller, DVD controller,.etc) .
Data Communication
Wireline Communication: 10/100 Based-T, xDSL, Gigabit Ethernet,.. Etc
Wireless communication: BlueTooth, WLAN, 2G/3G/4G, WiMax, UWB, …,etc

29. Outline Introduction What is SoC ? SoC characteristics
Benefits and drawbacks
Solution
Major SoC Applications
Summary

30. Summary
Technological advances mean that complete systems can now be implemented on a single chip .
The benefits that this brings are significant in terms of speed , area and power .
The drawbacks are that these systems are extremely complex requiring amounts of verification .
The solution is to design and verify re-useable IP .

31. SoC Trends The SoC Paradigm and Key Trends Time to Market Pressure
Design Complexity Issues
Deep Submicron Effects

32. Moore’s Law and Technology Scaling

33. ITRS Roadmap

34. Accelerated IC Process Technology

35. SoC Paradigm

36. SoC Co-Design Flow

37. SoC: At the Heart of Conflicting Trends

38. Ths SoC Challenges and Key Enablers

39. Evolutionary Problems
Key Challenges
Improve productivity
HW/SW codesign, Transaction-Level Modeling
Integration of analog & RF Ips
Improved DFT
Evolutionary techniques:
IP (Intellectual Property) based design
Platform-based design

40. SoC Economic Trends: Mask NRE

41. Productivity Gap

42. ASIC v.s. FPGA Complexity

43. Key Trends ASIC/ASSP (application-specific standard-product) ratio:
80/20 in 2000, 50/50 now
In-house ASIC design is down
Replaced by off-the-shelf, programmable ASSP
Number embedded processors in SoC rising:
ST: recordable DVD 5
Hughes: set-top box 7
Agere: Wireless base station 8
ST: HDTV platform 8
Latest mobile handsets 10
NEC: Image processor 128
ST: NPU >150

44. IP Reuse and IP-Based SoC Design

45. SoC Design + Rising Complexity = New Challenges

46. Key Trends: Embedded S/W Content in SoC is Way Up
eS/W: Current application complexity
Set-top box: >1 million lines of code
Digital audio processing: >1 million lines of code
Recordable DVD: Over 100 person-years effort
Hard-disk drive: Over 100 person-years effort
In multimedia systems
S/W cost (licenses) 6X larger than H/W chip cost
eS/W uses 50% to 80% of design resources
eS/W now an essential part of SoC products

47. Current Practice
Heterogeneous multi-processor SoCs are already current practice
Problem is that each system is an ad-hoc solution: reaching complexity barrier
Little flexibility
No effective programming model
Lots of low-level programming
Poor SW productivity
Code not portable

48. Next-Generation SoC Platforms Key Objectives
Flexibility: amortize NRE over more products
‘Softer’ systems: eFPGA, eSoG, eProcessors, combined with standard H/W IP (I/O, peripherals)
Fast platform implementation
Use of synthesizable, off-the-shelf IP components
Scalable SoC interconnect
Trend towards standardized platforms
Fast time-to-market for platform user
Need clean programming model
Shield architecture complexity

49. Networks on a chip

50. SoC for DVB

51. Network Processor