1. Kris Gaj Office hours: Monday, 6:00-7:00 PM, Tuesday 7:30-8:30 PM, Thursday, 4:30-5:30 PM, and by appointment Research and teaching interests: cryptography computer arithmetic FPGA design and verification Contact: Engineering Bldg., room 3225 kgaj@gmu.edu (703) 993-1575

2. ECE 645 Part of: MS in EE MS in CpE Digital Systems Design – pre-approved course Other concentration areas – elective course Certificate in VLSI Design/Manufacturing PhD in IT PhD in ECE

3. DIGITAL SYSTEMS DESIGN 1. ECE 545 Digital System Design with VHDL – K. Gaj, project, FPGA design with VHDL, Xilinx & Altera FPGAs 2. ECE 645 Computer Arithmetic – K. Gaj, project, FPGA design with VHDL, Xilinx & Altera FPGAs 3. ECE 586 Digital Integrated Circuits – D. Ioannou, homework/small projects 4. ECE 681 VLSI Design for ASICs – TK Ramesh, project/lab, front-end and back-end ASIC design with Synopsys tools 5. ECE 682 VLSI Test Concepts – T. Storey, homework

4. Prerequisites Permission of the instructor, granted assuming that you know RTL design with VHDL High level programming language (preferably C) ECE 545 Digital System Design with VHDL or

5. Prerequisite knowledge This class assumes proficiency with FPGA CAD tools from ECE 545 You are expected to be proficient with: –Synthesizable VHDL coding –Advanced VHDL testbenches, including file input/output –FPGA synthesis and post-synthesis simulation –FPGA implementation and timing simulation –Reading and interpreting all synthesis and implementation reports

6. Course web page ECE web page  Courses  Course web pages  ECE 645 http://ece.gmu.edu/coursewebpages/ECE/ECE645/S12/

7. Computer Arithmetic LectureProject Project 1 20 % Project 2 30 % Homework 10 % Midterm exam (in class) 15 % Final Exam (in class) 25 %

8. Advanced digital circuit design course covering addition and subtraction multiplication division and modular reduction exponentiation Efficient Integers unsigned and signed Real numbers fixed point single and double precision floating point Elements of the Galois field GF(2 n ) polynomial base

9. 1.Applications of computer arithmetic algorithms. INTRODUCTION Lecture topics

10. 1.Basic addition, subtraction, and counting 2.Addition in Xilinx and Altera FPGAs 3. Carry-lookahead, carry-select, and hybrid adders 4. Adders based on Parallel Prefix Networks 5. Pipelined Adders ADDITION AND SUBTRACTION

11. MULTIOPERAND ADDITION 1.Sequential multi-operand adders 2.Carry Save Adders 3.Wallace and Dadda Trees

12. Unsigned Integers Signed Integers Fixed-point real numbers Floating-point real numbers Elements of the Galois Field GF(2 n ) NUMBER REPRESENTATIONS

13. LONG INTEGER ARITHMETIC 1.Modular Multiplication 2.Modular Exponentiation 3.Montgomery Multipliers and Exponentiation Units

14. MULTIPLICATION 1.Tree and array multipliers 2.Unsigned vs. signed multipliers 3.Optimizations for squaring 4. Sequential multipliers - radix-2 multiplier - multipliers based on carry-save adders - radix-4 & radix-8 multipliers - Booth multipliers - serial multipliers

15. TECHNOLOGY 1.Embedded resources of Xilinx and Altera FPGAs - block memories - multipliers - DSP units 2. Multiplication in Xilinx and Altera FPGAs - using distributed logic - using embedded multipliers - using DSP blocks 3. Pipelined multipliers

16. DIVISION 1.Basic restoring and non-restoring sequential dividers 2. SRT and high-radix dividers 3. Array dividers

17. FLOATING POINT AND GALOIS FIELD ARITHMETIC 1.Floating-point units 2. Galois Field GF(2 n ) units

18. Literature (1) Required textbook: Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design, 2 nd edition, Oxford University Press, 2010.

19. Literature (2) Jean-Pierre Deschamps, Gery Jean Antoine Bioul, Gustavo D. Sutter, Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems, Wiley-Interscience, 2006. Milos D. Ercegovac and Tomas Lang Digital Arithmetic, Morgan Kaufmann Publishers, 2004. Isreal Koren, Computer Arithmetic Algorithms, 2nd edition, A. K. Peters, Natick, MA, 2002. Recommended textbooks:

20. Literature (2) 1.Pong P. Chu, RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability, Wiley-IEEE Press, 2006. 2.Volnei A. Pedroni, Circuit Design and Simulation with VHDL, 2 nd edition, The MIT Press, 2010. 3. Sundar Rajan, Essential VHDL: RTL Synthesis Done Right, S & G Publishing, 1998. VHDL books:

21. Literature (3) Supplementary books: 1.E. E. Swartzlander, Jr., Computer Arithmetic, vols. I and II, IEEE Computer Society Press, 1990. 2. Alfred J. Menezes, Paul C. van Oorschot, and Scott A. Vanstone, Handbook of Applied Cryptology, Chapter 14, Efficient Implementation, CRC Press, Inc., 1998.

22. Literature (3) Proceedings of conferences ARITH - International Symposium on Computer Arithmetic ASIL - Asilomar Conference on Signals, Systems, and Computers ICCD - International Conference on Computer Design CHES - Workshop on Cryptographic Hardware and Embedded Systems Journals and periodicals IEEE Transactions on Computers, in particular special issues on computer arithmetic. IEEE Transactions on Circuits and Systems IEEE Transactions on Very Large Scale Integration IEE Proceedings: Computer and Digital Techniques Journal of Signal Processing Systems

23. Homework reading assignments analysis of computer arithmetic algorithms and implementations design of small hardware units using VHDL

24. Midterm exams Midterm Exam - 2 hrs 30 minutes, in class multiple choice + short problems Final Exam – 2 hrs 45 minutes comprehensive conceptual questions analysis and design of arithmetic units Practice exams on the web Midterm Exam - Monday, March 26 Final Exam - Monday, May 14, 7:30-10:15 PM Tentative days of exams:

25. Project 1 Project I (individual, 20% of grade) Adders in Xilinx and Altera FPGAs Final report & deliverables due Monday, March 19 Choosing optimal architecture for combinational adder pipelined adder in Xilinx FPGAs (Virtex 5 & Virtex 6) Altera FPGAs (Stratix III & Stratix IV) ASICs (bonus) Done individually

26. Project 2 Project II (in groups of two or individually, 30% of grade) Modular Exponentiation of Large Integers or Floating Point Operations Final report & deliverables due Monday, May 7 Investigation of alternative architectures for the best performance in terms of Latency Latency x Area product in Xilinx FPGAs (Virtex 5 & Virtex 6) Altera FPGAs (Stratix III & Stratix IV) ASICs (bonus)

27. Primary applications (1) Execution units of general purpose microprocessors Integer units Floating point units Integers (8, 16, 32, 64 bits) Real numbers (32, 64 bits)

28. Primary applications (2) Digital signal and digital image processing Real or complex numbers (fixed-point or floating point) e.g., digital filters Discrete Fourier Transform Discrete Hilbert Transform General purpose DSP processors Specialized circuits

29. Primary applications (3) Coding Elements of the Galois fields GF(2 n ) (4-64 bits) Error detection codes Error correcting codes

30. Secret-key (Symmetric) Cryptosystems key of Alice and Bob - K AB Alice Bob Network Encryption Decryption

31. Hash Function arbitrary length message hash function hash valueh(m) h m fixed length It is computationally infeasible to find such m and m’ that h(m)=h(m’)

32. Primary applications (4) Cryptography Integers (16, 32, 64 bits) IDEA, RC6, Mars, SHA-3 candidates: SIMD, Shabal, Skein, BLAKE Twofish, Rijndael, SHA-3 candidates Elements of the Galois field GF(2 n ) (4, 8 bits)

33. RC6 MARS Twofish MUL32, 2 x ROL32, S-box 9x32 Main operations Auxiliary operations XOR, ADD/SUB32 2 x SQR32, 2 x ROL32 XOR, ADD/SUB32 96 S-box 4x4, 24 MUL GF(2 8 ) XOR ADD32 Rijndael Serpent 8 x 32 S-box 4x4 XOR 16 S-box 8x8 24 MUL GF(2 8 ) XOR

34. 34 Basic Operations of 14 SHA-3 Candidates 34 NTT – Number Theoretic Transform, GF MUL – Galois Field multiplication, MUL – integer multiplication, mADDn – multioperand addition with n operands

35. Public Key (Asymmetric) Cryptosystems Public key of Bob - K B Private key of Bob - k B Alice Bob Network Encryption Decryption

36. RSA as a trap-door one-way function M C = f(M) = M e mod N C M = f -1 (C) = C d mod N PUBLIC KEY PRIVATE KEY N = P  Q P, Q - large prime numbers e  d  1 mod ((P-1)(Q-1))

37. RSA keys PUBLIC KEY PRIVATE KEY { e, N } { d, P, Q } N = P  Q e  d  1 mod ((P-1)(Q-1)) P, Q - large prime numbers

38. Primary applications (5) Cryptography Long integers (1k-16k bits) Public key cryptography RSA, DSA, Diffie-Hellman Elliptic Curve Cryptosystems, Pairing Based Cryptosystems Elements of the Galois field GF(2 n ) (160-512 bits)

39. Primary applications (5) Cipher Breaking Public key cryptography RSA PUBLIC KEY RSA PRIVATE KEY { e, N } { d, P, Q } N = P  Q P, Q e  d  1 mod ((P-1)(Q-1))