1. Bridging Router Performance and Queuing Theory N. Hohn*, D. Veitch*, K. Papagiannaki, C. Diot *: University of Melbourne This work appeared at ACM Sigmetrics 2004

2. 2 Motivation End-to-end packet delay is an important metric for performance and SLAs Building block of end-to-end delay is through router delay We measure the delays incurred by all packets crossing a single router

3. 3 Overview Full Router Monitoring Delay Analysis and Modeling Delay Performance: Understanding and Reporting

4. 4 Measurement Environment

5. 5 Packet matching SetLinkMatched pkts% traffic C2- out C4In2159870.03% C1In703760.01% BB1In34579662247.00% BB2In38915377252.89% C2out73523675799.93%

6. 6 Overview Full Router Monitoring Delay Analysis and Modeling Delay Performance: Understanding and Reporting

7. 7 Store & Forward Datapath Store: storage in input linecard’s memory Forwarding decision Storage in dedicated Virtual Output Queue (VOQ) Decomposition into fixed-size cells Transmission through switch fabric cell by cell Packet reconstruction Forward: Output link scheduler Not part of the system

8. 8 Delays: 1 minute summary

9. 9 Store & Forward Datapath Store: storage in input linecard’s memory Forwarding decision Storage in dedicated Virtual Output Queue (VOQ) Decomposition into fixed-size cells Transmission through switch fabric cell by cell Packet reconstruction Forward: Output link scheduler Not part of the system Δ(L)

10. 10 Minimum Transit Time Packet size dependent minimum delay Δ(L), specific to router architecture and linecard technology

11. 11 Store & Forward Datapath Store: storage in input linecard’s memory Forwarding decision Storage in dedicated Virtual Output Queue (VOQ) Decomposition into fixed-size cells Transmission through switch fabric cell by cell Packet reconstruction Forward: Output link scheduler Not part of the system Δ(L) FIFO queue

12. 12 Modeling

13. 13 Modeling Fluid queue with a delay element at the front

14. 14 Model Validation

15. 15 Error as a function of time

16. 16 Modeling results Our crude model performs well Use effective link bandwidth (account for encapsulation) Small gap between router performance and queueing theory! The model defines Busy Periods: time between the arrival of a packet to the empty system and the time when the system becomes empty again.

17. 17 Overview Full Router Monitoring Delay Analysis and Modeling Delay Performance: Understanding and Reporting

18. 18 On the Delay Performance SNMP utilization not sufficient to predict delay Model allows for router performance evaluation when arrival patterns are known Goal: metrics that Capture operational-router performance Can answer performance questions directly Busy Period structures contain all delay information

19. 19 Busy periods metrics tsts D A

20. 20 Property of significant BPs

21. 21 Triangular Model

22. 22 Issues Report (A,D) measurements There are millions of busy periods even on a lightly utilized router Interesting episodes are rare and last for a very small amount of time

23. 23 Report BP joint distribution

24. 24 Duration of Congestion Level-L

25. 25 Conclusion Results Full router empirical study Delay modeling Reporting performance metrics

26. Thank you! dina.papagiannaki@intel.com