1. Error Patterns in MLC NAND Flash Memory: Measurement, Characterization, and Analysis
Yu Cai1, Erich F. Haratsch2 , Onur Mutlu1 and Ken Mai1
DSSC, ECE Department, Carnegie Mellon University
LSI Corporation

2. Evolution of NAND Flash Memory
CMOS scaling
More bits per Cell
Seaung Suk Lee, “Emerging Challenges in NAND Flash Technology”, Flash Summit 2011 (Hynix)
Flash memory widening its range of applications
Portable consumer devices, laptop PCs and enterprise servers

3. Reliability and Endurance Challenges for NAND Flash Memories
Endurance continues to deteriorate
Only a few thousand reliable P/E cycles of NAND Flash memory
Error correction capability requirements of ECC keep increasing
Big gap between MLC flash endurance and storage reliability requirements
Enterprise storage needs >50k P/E cycles

4. Future NAND Flash Storage Architecture
Memory
Signal
Processing
Raw Bit
Error Rate
Noisy
Error
Correction
BER < 10-15
Read voltage adjusting
Data scrambler
Data recovery
Soft-information estimation
Hamming codes
BCH codes
Reed-Solomon codes
LDPC codes
Other Flash friendly codes
Need to understand NAND flash error patterns

5. Test System Infrastructure
Algorithms
Wear Leveling
Address Mapping
Garbage Collection
ECC
(BCH, RS, LDPC)
Reset
Erase block
Program page
Read page
Control
Firmware
Signal Processing
Software Platform
USB
PHYChip
FPGA
USB controller
NAND
Controller
Flash
Memories
USB Driver
Host USB PHY
Host Computer
USB Daughter Board
Mother Board
Flash Board

6. NAND Flash Testing Platform
USB Daughter Board
USB Jack
HAPS-52 Mother Board
Virtex-II Pro
(USB controller)
3x-nm
NAND Flash
Virtex-V FPGA
(NAND Controller)
NAND Daughter Board

7. NAND Flash Usage and Error Model
Erase Errors
Program Errors
P/E cycle 0
P/E cycle i
Start …
P/E cycle n
End of life
Erase
Block
Program
Page
(Page0 - Page128)
Read Errors
Retention Errors
Retention1
(t1 days)
Read
Page
Retention Errors …
Read Errors 13
lots of diagrams of boxes and text, need to find a way to differentiate them
Retention j
(tj days)
Read
Page

8. Testing Methodology Erase errors Program interference errors
Count the number of cells that fail to be erased to “11” state
Program interference errors
Compare the data immediately after page programming and the data after the whole block being programmed
Read errors
Continuously read a given block and compare the data between consecutive read sequences
Retention errors
Compare the data read before retention and after retention
Characterize short term retention errors under room temperature
Characterize long term retention errors by baking in the oven under 125℃

9. Flash Error Rates Comparison
retention errors
long retention time data is from accelerated testing
Error rate increases with P/E cycles
Retention errors are the most dominant errors
Retention error rates increase as retention time increase

10. Retention Error Mechanism
LSB/MSB
Stress Induced Leakage Current (SILC)
Floating
Gate
REF1
REF2
REF3 11 10 01 00
Vth
Erased
Fully programmed 16
explain what the diagram is showing
animate in distribution spread
Electrons loss from the floating gate causes retention errors
Cells with more programmed electrons suffer more from retention errors
Threshold voltage is more likely to shift one interval than multiple intervals

11. Retention Error Value Dependency (3 months)
00 01
01 10
Cells with more programmed electrons tend to suffer more from retention noise (i.e. 00 and 01)

12. 2-bit MLC Background Overview
Internal Architecture of 2-bit NAND Flash Memory
LSB-Even Page Sets
MSB-Even Page Sets
MSB-Odd Page Sets
LSB-Odd Page Sets

13. Retention Error Location Dependency
LSB page has less BER
Even pages have less BER 18
note log scale on y-axis
use same/similar even/odd diagram as before
Odd Page Cells
Even Page Cells
REF1
REF2
REF3
LSB/MSB 11 10 01 00
Vth

14. Program interference
LSB/MSB
Additional Electrons Injected
Floating
Gate
REF1
REF2
REF3 11 10 01 00 VT
Erased
Fully programmed
Program interference errors are caused by extra electrons injection when programming neighbor cells
Cells with less programmed electrons suffer more from interference errors
Threshold voltage is less likely to shift up more than one level

15. Program Interference Error Value Dependency
11  10
10  01
Cells with less programmed electrons tend to suffer more from neighboring cell interference (i.e. 11 and 10)

16. Program Interference Error Location Dependency
Program interference errors appear in even-MSB pages
BER of bottom pages are orders of magnitude higher

17. Write Interference on bottom wordline
0 V
Vpass(10V)
Vpgm(20V)
Vpass(10V)
Vdd
Vdd
SGS
WL0
WL n
WL31
SGD
bitline … …
GND -
10 V
0 V
Channel Voltage
Potential of drain edge of SGS transistor is raised by channel boosting
Electrons are accelerated between SGS and WL0 and are quite possible to injected into the floating gate of WL0
HCI noise generated by source/drain hot-electrons in WL0
Threshold voltage of cells on WL0 shift right and it can even shift across more than one level (e.g. 11->01 or 00)

18. Read Error Analysis 11 10 01 00 Floating Gate REF1 REF2 REF3 VT Erased
Fully programmed

19. Erase Errors Analysis
0 V 24
weird capitalization in plot legend
maybe need diagram to show what is going on?
Continuous erases can significantly reduce errors
remove residual electrons n+ n+
+18 V

20. Conclusions & Future work
Flash errors could show up for any operations
Erase error, program error, retention error and read error
Retention errors are the most dominant errors
Flash errors show explainable error patterns
Cycle-dependency, value-dependency and location-dependency
Understanding of modern flash memory error patterns will enable designing effective error tolerance mechanisms
Value-asymmetry aware coding techniques
Cell location-aware wear leveling mechanisms