1. LKr readout: present and future R. Fantechi 30/8/2012

2. Present: SLM readout during dry and technical runs

3. Hardware - 1 Power supplies – Despite a first positive attempt to switch on racks 7 and 8 with the old power supplies, the second one was negative All old power supplies not working, even the two for the clock distribution crates – New power supplies moved to the crates in racks 7-8 + clock Thanks to Phil for the help Positive operation for long periods Fuses on power distribution boxes to be changed (need now 16 A) – 11 power supplies available Need rethinking of the CPD layout for the Technical run See later…

4. Hardware - 2 Trigger supervisor (NA48 legacy) – As already explained, the idea was to restart the complete system (rack 7-8, trigger supervisor, SLM PCs) as it was in 2010. Have a reference system to test the new trigger distribution – The trigger supervisor was working, but… 30 calibration trigger sent, 260K received However with reasonable content in terms of trigger word and timestamp, no funny data – Some time spent to understand the bad behaviour Old experts consulted No way Decided to go straight to the new trigger distribution

5. Hardware - 3 Trigger distribution (NA62 way) – Use a TALK board with a test TAXI receiver and a logic state analyzer Compare the data received from the old TS with the ones from the TALK: same structure and sequence – The same reading the TAXI FIFO in the trigger receiver Read correctly the data from the TALK board – Connect the TALK output to the LKr trigger receiver Run the standard LKRSBC software Data are transferred to the SLM Time to tune the PC readout software – All this done when the dry run was already advanced, as soon as the trigger distribution has been debugged

6. Software (from last meeting) Slm_scheduler – Used in each PC to start/stop the relevant readout processes after a run control interaction – Ready, tested with a run control simulator – To be tested with the real run control test done, to be done with multiple copies and real readout program Run control to harness interface – Needed because the LKr hw control is still in the NA48 style – It is just a translator of run control command from NA62 to NA48 style – Code written, to be tested – tested standalone, to be done with the harness Timestamp collection – Read timestamp from the TALK board at EOB, write them on a file to be read by all the readout processes – To be written, template exists working, started at sys startup

7. Software Readout software – First occasion to test the mods by Christina Timestamp matching, zero suppression, new format – Test almost completed, several small bugs fixed The actual triggers are basically random ones, no calibration pulses, only pedestals So no easy way to test the zero suppression feature Otherwise pedestal data have been readout from all the available CPDs in rack 7 and 8 Files available – A program by Christina to decode the new format has been implemented to make histograms and for a first evaluation of noise.

8. Looking forward the technical run CPD configuration – Move from the 5120 channel configuration to a 4096 one (64*64 cells around the center) This will leave one spare power supply See Giuseppe’s talk for the physics interest – Investigation will start for a possible use of the transceiver sums to have a coarse coverage of all the calorimeter 2*8 sums done analogically inside the transceivers The same type of cables to the CPD (but they are hidden below the false floor….) One additional CPD should host almost all the sums (512 out of 570, for the channels not read individually) Use the spare supply – Two main goals: Read the entire calorimeter in 2012 Have a way to check now if all the channels are ok: could be done later with an oscilloscope when the old system will be dismounted and the cables will be free. May be to late?

9. Looking forward the technical run Hardware – Install power supplies for the selected area – Change fuses – Configure the Fastbus branch structure accordingly – Test all CPDs and CPDAS cards and make repairs – Resurrect the CPD configuration database – Configure the calibration trigger – Adjust the delays for calibration and physics triggers – Configure the connections between SLMs and PCs – Configure the data output links on the SLM PCs – Commissioning of the new UPS for the readout The old broke down during the dry run… No way to repair it, just anticipate the installation of the new one.

10. Looking forward the technical run Software – Firmware adjustments for the trigger transmission – Tune the operation of slm_scheduler and rctoharness – Test the zero suppression mechanism – Little implementation of the timestamp distribution Add the transmission of the trigger word And consequently modify the class setup by Christina Get rid of the 9 fake triggers sent to the CPDs – Implement the protocol to receive L1 requests and transmit data – Implement the SLM decoding inside NA62Reconstruction – Monitor software

11. Future: CREAM readout

12. Work at CAEN Main focus in the last months – Board layout – DDR3 simulation – To choose between 1 8GB DDR or 2 4GB DDR modules Impact on the board layout As the main access to the DDR is for small blocks, it is needed to check the timing – Decision taken for 1 DDR module PCB designers working all along August to develop the PCB – The daughter board layout and connections has been freezed – The communication firmware for the prototype will be the standard TCP/IP suite implemented on a NIOS processor But for the production we have to define the proper “fast” protocol to read data at L1

13. This means a 3.2  s window 128 samples written in the circular buffer in 1.5  s Evaluation to be completed with random L0/L1, now periodic

17. Daughter board PCB – side a

18. Daughter board PCB – side b

19. Plans – The prototypes will be available at CERN not before mid October Some clash with the technical run Will it be possible to have some test with beam in the last period? It depends obviously by how many problems will be found in the debugging Setup of the test bench to start soon Stefano Venditti in PH/ESE starting October 1 st – Crates and VME bridges ordered One crate already at CERN for evaluation – Production of the prototype clock distribution board now