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MSP432™ MCUs Training Part 2: Cortex M4F Core

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Presentation on theme: "MSP432™ MCUs Training Part 2: Cortex M4F Core"— Presentation transcript:

1 MSP432™ MCUs Training Part 2: Cortex M4F Core
Welcome to the MSP432 MCU Training. This is Part 2 and we will take a look at the Cortex M4F Core.

2 MSP432 | 32-bit Cortex-M4F 32-bit pipeline architecture
Cortex-M4 with DSP extension instruction set Floating Point Unit Standard Cortex-M Debugger Module, Serial Wire Debug, ITM Trace support Core modules including DMA, SysTick, & Interrupt (NVIC) The MSP 432 uses a 32-bit Cortex-M4F CPU. The CPU has a 32-bit data path 32 bit register bank and 32 bit memory interfaces. The CPU uses a Harvard architecture which means that it has a separate instruction BUS and data BUS. This allows the instructions and data accesses to take place at the same time and as a result of this the performance of the processor increases because the data accesses do not affect or interfere with the instruction pipeline. This feature results in multiple BUS's and interfaces across the Cortex - M4F each with optimize uses and the ability to be used simultaneously. However, the instruction in data BUS share the same memory space called the unified memory system. So with this particular Cortex-M4F flavor that was chosen by the MSP432 the device also includes a nested vector interrupt controller for short NVIC. It also includes an FPU, Floating Point Unit as well as the enhanced DSP instruction set that comes with the Cortex-M4. From the debugger standpoint it features a standardized Cortex-M debugger module, a COI Debug, as well as ITM trace support. Since this is a Cortex it also inherits a number of peripherals that come from the Cortex and ARM family including the Micro DMA, SysTick and Interrupt as mentioned before

3 Cortex-M | Core Comparison
Thumb Thumb-2 HW MPY HW DIV Saturated math DSP-exten sions FPU ARM architecture Cortex-M0 Most Subset 1 or 32 cycle No ARMv6-M Von Neumann Cortex-M0+ Cortex-M1 3 or 33 cycle Cortex-M3 Entire 1 cycle 2-12 cycles Yes ARMv7-M Harvard Cortex-M4 Optional Yes for MSP432 ARMv7E-M This slide gives you an overview to compare the different flavors of the Cortex M cores, starting from Cortex M0 to Cortex M4. As you can see as we increase the complexity in the core, more instructions have been added to the instruction set as well as other additional feature as hardware multiplier, hardware divider, saturated math capabilities, DSP instruction extension, as well as a Floating Point Unit. You might also notice that moving from Cortex M0 and M0+ to M3 & M4 the ARM architecture changes from Von Neumann to Harvard which adds an additional data BUS in addition to the instruction BUS. The reason why Cortex -M4F was chosen for MSP432 is because it adds more performance and capabilities while adding minimal additional power consumption. This will be shown in the next slides showing the results of Cortex M4Fbeing used on MSP432

4 FPU | Floating-Point Unit
The FPU provides floating-point computation functionality that is compliant with the IEEE 754 standard Enables conversions between fixed-point and floating-point data formats, and floating-point constant instructions The Cortex-M4F FPU fully supports single-precision: Add Subtract Multiply Divide Single cycle multiply and accumulate (MAC) Square root Lastly the Floating Point Units is another addition to the Cortex M4F version chosen by the MSP432 family. The Cortex M4F FPU fully supports addition, subtraction, multiplication, division and square root and so on. One thing to note is that FPU support is already enabled automatically in most of the compilers so without a single click you can already use floating point in your operations with MSP432. Modes of Operation...

5 MSP432 | CoreMark = 3.41CM/MHz Core Device CoreMark Cortex-M4 MSP432
3.40. Competitor A 3.34 [168MHz-Ohs, --no_size_constraints] Cortex-M3 2.98 Competitor B 2.15 Cortex-M0+ Competitor C 2.28 2.07 Test Conditions Number measured with IAR 3MHz, Active Mode with VCORE=0 Since msp432 uses a standardized core, it would be good to measure its performance in a standardized way. Core Mark is a standardized benchmark that is used to measure the performance of the processor core. The Core Mark was developed by the Embedded Microcontroller Benchmark Consortium EMBBC to help system designers select the most optimal processors and understand the performance and energy characteristics of the systems. MSO432 essentially scores the highest possible score achievable on a Cortex-M4F platform. We know that this is the highest score because we know that this is the score an ideal Cortex-M4F core implementation can achieve. This is the same information that is shown on the Cortex-M4F page on the ARM website. *Source: MSP-Benchmark twiki

6 ULPBench EEMBC’s ULPBench provides a true comparison of microcontroller current consumption and efficiency 153.3 TBD 119 90% better score than our closest competitor! In addition to CoreMArk EMMBC also developed another benchmark that measures the energy efficiency of Ultra Low Power microcontrollers. ULP Bench will include a set of test that measures the device's energy consumption when performing a predefined task that is applicable to ULP applications. ULP Bench was released in late 2014 and since then has become a standard low energy benchmark for the wide range of microcontrollers in the industry. So the benchmark is measured as follows: Usually a task involves the microcontroller to wake up once per second to execute a predefined workload. Once it is completed the microcontroller needs to go back to sleep and wake up one second later. The overall energy consumed by the entire system to accomplish the task is measured over this one second period. As a result, the lower the energy consumed, the better you are as a microcontroller and as a system. To make the score a little bit more intuitive for the readers, the score is actually calculated by using one thousand and then divided by the total energy consumption measured in micro joules. As you can see the result is actually quite impressive for MSP devices. From the graph the MSP432 achieves the Highest ULPBench score in the world today of and it is better than competition ranging from Cortex -M4, Cortex -M3 and all the way down to Cortex-M0+ as well as other proprietary architecture. This goes to show that performance doesn’t always require more power and when implemented correctly, a higher performance Core such as the Cortex-M4F can still yield lower power than other simplified cores. So this concludes the part 2 of the MSP432 training series. In the next parts of the training series we will uncover what was done to the design of the device, the power system, the clocking structure, the intelligent peripherals, the software tools, debuggers all were developed to achieve the world's lowest energy microcontroller for Cortex-M4 and achieve the highest score on ULP Bench. Thanks for watching.

7 Cortex-M Interrupt Nested Vector Interrupt Controller (NVIC)

8 Interrupts | Nested Vectored Interrupt Controller (NVIC)
Handles exceptions and interrupts 8 programmable priority levels, priority grouping 7 exceptions and 71 Interrupts Automatic state saving and restoring: R0–R3, R12, LR, PSR, and PC Automatic reading of the vector table entry Pre-emptive/Nested Interrupts Tail-chaining Deterministic: always 12 cycles or 6 with tail-chaining ADC interrupt The MSP432 Nested Vectored Interrupt Controller, or NVIC, is tightly coupled to the central processing unit. It handles all of the exceptions and interrupts that come into the CPU. There are eight programmable priority levels and priority grouping. In most microcontroller interrupt vector tables, the priority levels for each peripheral are set by the manufacturer, and you have no input into what they are. That's not the case on this device. You can reprogram the priorities as you like. This device has 7 system level exceptions and 65 peripheral interrupts. It has automatic state save and restore for entering and exiting Interrupt Service Routines, as well as automatic reading of the vector table entry to quickly facilitate this process. One of the first rules that you learn when programming interrupts on a microcontroller is to not nest interrupts, but sometimes you need to nest the interrupts. For instance, you need to get to a very low latency motor control or device. You need to get to it very quickly, and you have other interrupts that take too long. Those long ISRs will need to be interruptible. On most microcontrollers you will have to program this tedious process in software. On the MSP432 devices, you can do it by programming the NVIC hardware. You can make interrupts preemptive, and you can nest them. Interrupts can also be tail-chained, which is something I'll explain in the next few slides. Interrupts are deterministic. They're always either 12 cycles or 6 cycles if they're tail-chained. Taking a look at the diagram at the bottom, we can see this is an application with a two interrupts. From left to the right, the first interrupt that goes off is for motor control. Motor control requires extremely low latency. You can't wait. You must act on the interrupt quickly. The second interrupt is a repeat of the first. In the third instance, a communication interrupt like the USCI has started operation. Communication interrupts using involve FIFO’s and buffers, so they can wait. When the motor control interrupt arrives, we can't wait for the communications ISR to complete, the motor control ISR must preempt it. The remaining instances are further examples. Remember that the nesting behavior is programmed into the NVIC hardware. Entry Automatically pushes registers R0–R3, R12, LR, PSR, and PC onto the stack In parallel, ISR is pre-fetched on the instruction bus. ISR ready to start executing as soon as stack PUSH complete Exit Processor state is automatically restored from the stack In parallel, interrupted instruction is pre-fetched ready for execution upon completion of stack POP Timer_A interrupt Main application (foreground) t

9 Interrupts | Latency: Tail Chaining
Highest Priority IRQ1 IRQ2 PUSH ISR 1 POP PUSH ISR 2 POP Typical processor Tail-chaining Cortex M4 Interrupt handling in HW PUSH ISR 1 ISR 2 POP Tail-chaining reduces interrupt latency. In this diagram, two interrupts go off at the same time: IRQ1, which is the higher priority, and IRQ2. In a typical processor, the state of the processor would be pushed onto the stack, the highest priority interrupt service routine would run, the state of the processor would be popped off the stack. At this point the interrupt controller would detect that there was another interrupt pending, and repeat the process for the lower priority interrupt. Note that the pop and the push right in the middle are doing the exact same thing but in opposite directions … there's really no need to do those. Cortex M4 interrupt handling is done in hardware. We have a very short push at the beginning, and then we see that ISR1 runs. The NVIC detects that another interrupt is pending … it simply transfers execution to the pending interrupt's ISR. This process takes 6 cycles. When the second ISR completes and no other interrupts are pending, the state of the processor is restored. This will result a significant decrease in interrupt latency in the typical interrupt driven system. tail chaining can also be useful in other interrupt scenarios, such as pre-emptive and late arrival 12 Cycles 6 Cycles 12 Cycles Saving 18 cycles: 24 cycles (POP + PUSH)  6 cycles (Tail-chaining)

10 Interrupts | Declaration on MSP432
Option 1: Declare the entire Interrupt Vector table Option 2: MSP430 method Use #pragma vector #pragma vector = USCI_B0_VECTOR __interrupt void USCI_B0_ISR(void) { switch(__even_in_range(UCB0IV,12)) case 0: break; …… } //All unused interrupts trapped #pragma vector = unused_interrupts __interrupt void intDefaultHandler(void) //trap msp432_startup_ccs.c ISR Handlers: stubs defined in table. Treated as regular function, code in user’s application MSP430 code re-use Interrupt vector & handler function defined together

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