1. CMOS Detector Technology
Markus Loose
Rockwell Scientific
Alan Hoffman
Raytheon Vision Systems
Vyshnavi Suntharalingam
MIT Lincoln Laboratory
Scientific Detector Workshop, Sicily 2005

2. General CMOS Detector Concept
CCD Approach
CMOS Approach
Pixel
Charge generation &
charge integration
Charge generation, charge integration & charge-to-voltage conversion +
Photodiode
Amplifier
Array Readout
Charge transfer from pixel to pixel
Multiplexing of pixel voltages: Successively connect amplifiers to common bus
Sensor Output
Output amplifier performs charge-to-voltage conversion
Various options possible:
no further circuitry (analog out)
add. amplifiers (analog output)
A/D conversion (digital output)

3. Common CMOS Features
CMOS sensors/multiplexers utilize the same process as modern microchips
Many foundries available worldwide
Cost efficient
Latest processes available down to 0.13 µm
CMOS process enables integration of many additional features
Various pixel circuits from 3 transistors up to many 100 transistors per pixel
Random pixel access, windowing, subsampling and binning
Bias generation (DACs)
Analog signal processing (e.g. CDS, programmable gain, noise filter)
A/D conversion
Logic (timing control, digital signal processing, etc.)
Electronic shutter (snapshot, rolling shutter, non-destructive reads)
No mechanical shutter required
Low power consumption
Radiation tolerant (by process and by design)

4. Astronomy Application: Guiding
Special windowing can be used to perform full-field science integration in parallel with fast window reads.
Simultaneous guide operation and science data capture within the same detector.
Two methods possible:
Interleaved reading of full-field and window
No scanning restrictions or crosstalk issues
Overhead reduces full-field frame rate
Parallel reading of full-field and window
Requires additional output channel
Parallel read may cause crosstalk or conflict
No overhead  maintains maximum full-field frame rate
Full field row
Window
Full field row
Window

5. Stitching Enables Large Sensor Arrays
The small feature size of modern CMOS processes limits the maximum area that can be exposed in one step (so-called reticle) to about 22 mm.
However, larger chips can produced by breaking up the design into smaller sub-blocks that fit into the reticle.
Stitched CMOS Sensor
Sub-blocks are exposed one after another
Some blocks are used multiple times
Ultimate limit is given by wafer size
array
horiscan1
horiscan2 V 3 2 1
Reticle
array
horiscan1
horiscan2 V 3 2 1
22mm

6. Monolithic CMOS
A monolithic CMOS image sensor combines the photodiode and the readout circuitry in one piece of silicon
Photodiode and transistors share the area => less than 100% fill factor
Small pixels and large arrays can be produced at low cost => consumer
applications (digital cameras, cell phones, etc.)
3T Pixel
Reset
Select SF PD
Read Bus
photodiode
transistors
4T Pixel
Read Bus
Select SF
Pinned PD
Reset
p-sub n+ p+ TG

7. Complete Imaging Systems-on-a-Chip
Monolithic CMOS technology has enabled highly integrated, complete imaging systems-on-a-chip:
Single chip cameras for video and digital still photography
Performance has significantly improved over last decade and is better or comparable to CCDs for many applications.
Especially suited for high frame rate sensors (> Gigapixel/s) or other special features (windowing, high dynamic range, etc.)
2 Mpixel HDTV CMOS Sensor
However, monolithic CMOS is still limited with respect to quantum efficiency:
Photodiode is relatively shallow => low red response
Metal and dielectric layers on top of the diode absorb or reflect light => low overall QE
Backside illumination possible, but requires modification of CMOS process
Quantum Efficiency of a CMOS sensor
Si PIN
NIR AR coating
UV AR coating
3T pixel
w/ microlenses
photodiode
Microlenses increase fill factor:

8. Silicon Readout Integrated Circuit (ROIC)
Sensor Chip Assembly (SCA) Structure: Hybrid of Detector Array and ROIC Connected by Indium Bumps
Detector Array
Indium bump
Detector Array
Silicon Readout Integrated Circuit (ROIC)
Mature interconnect technique:
Over 4,000, indium bumps per SCA demonstrated
99.9% interconnect yield
16,000,000
Also called a Focal Plane Array (FPA) or Hybrid Array

9. CMOS SCA Revolution
Large CMOS hybrids revolutionized infrared astronomy
Growth in size has followed "Moore's Law" for over 20 years
18 month doubling time

10. Three Most Common Input Circuits for CMOS ROICs
SFD
(Source Follower per Detector)
also called "Self Integrator"
CTIA
(Capacitance Transimpedance Amplifier) DI
(Direct Injection)
Advantages
simple
low noise
low FET glow
low power
very linear
gain determined by ROIC design (Cfb)
detector bias remains constant
large well capacity
gain determined by ROIC design (Cint)
Disadvantages
gain fixed by detector and ROIC input capacitance
detector bias changes during integration
some nonlinearity
more complex circuit
FET glow
higher power
poor performance at low flux
Comments
Most common circuit in IR astronomy
Very high gains demonstrated
Standard circuit for high flux

11. Temperature and Wavelengths of High Performance Detector Materials
Si:As IBC
Si PIN
InGaAs
SWIR HgCdTe
LWIR HgCdTe
MWIR HgCdTe
InSb
Approximate detector temperatures for dark currents << 1 e-/sec

12. Detector Material Choices for CMOS Hybrid Arrays
Si PIN
InGaAs
HgCdTe:
1.7m
2.5 m
5.2 m
10 m
InSb
Si:As IBC
(BIB)
Spectral
Range*, m
0.4 – 1.0
0.9** – 1.7
0.9** – 2.5
0.9** – 5.2
5 – 10
0.4 – 5.2
5 – 28
Operating
Temp***, K
~ 200
~ 130
~ 140
~ 90
~ 50
~ 25?
~ 35
~ 7
General Comments
All detectors can have:
100% optical fill factor
100% internal QE (total QE depends on AR coat)
Exception: Si:As is 40-70% between 5 and 10 m
ROICs are interchangeable among detectors (except Si:As)
HgCdTe and InGaAs require special packaging due to CTE mismatch between detector and ROIC
* Long wave cutoff is defined as 50% QE point
** Spectral range can be extended into visible range by removing substrate
*** Approximate detector temperatures for dark currents << 1 e-/sec

13. Process Comparison CCD CMOS > 35 years of evolution
“Trailing edge” fabs
Economics of scale accelerate progress
Lower fabrication cost, Foundry access
High resistivity (deep depletion) substrates
Controlled temperature ramps & stress control
Epi doping optimized for digital CMOS
Scalable to 300mm
Buried channel
Multiple oxidation cycles
Complex implant engineering
Rapid Thermal Processing (RTP)
Single gate dielectric thickness
Multiple gate dielectric thicknesses
Doped polysilicon (single type)
Complementarily doped polysilicon
Silicided polysilicon and FET source/drain
Highly nonplanar surfaces
Conservative design rules
Fine-line patterning
Multiple metal layers (dense routing)
Vulnerable to space-radiation-induced traps
Highly suitable for long-term space-based applications
2mm
2mm
2mm
Four-Poly OTCCD
180-nm SRAM cell
Stacked via to poly

14. Limitations of Standard Bulk CMOS APS
Pixel Layout
Fill factor tradeoff
Photodetector and pixel transistors share same area
PD from Drain-Substrate or Well-Substrate diode
Low photoresponsivity
Shallow, heavily doped junctions
Limited depletion depth
Absorption and reflection in poly, metal, and oxide layers
Surface recombination at Si/SiO2 interface
QE*FF > 60% is good, many < 20%
High leakage
LOCOS/STI, salicide
Transistor short channel effects
Substrate bounce and transient coupling effects
RST
ROW
OUT
VDD
photodiode
p-epi
n-Well
p-well
Field Oxide
VDD p+
ROW
OUT n+
p+ Substrate
RST
Radiation effects
Interface state generation especially in stressed locations
Field inversion causing complete failure of the imager
Layout-related mitigation techniques limit pixel fill factor

15. Advantages of Vertical Integration
Conventional Monolithic APS
3-D Pixel
Light PD
pixel PD 3T
Addressing
pixel
ROIC
Processor
Addressing
A/D, CDS, …
Pixel electronics and detectors share area
Fill factor loss
Co-optimized fabrication
Control and support electronics placed outside of imaging area
100% fill factor detector
Fabrication optimized by layer function
Local image processing
Power and noise management
Scalable to large-area focal planes

16. Approaches to 3D Integration
(To Scale)
Tier-1
3D-Vias
3D-Vias
10 mm
Tier-2
Slide showing “to scale” several different approaches to 3D circuit integration. Including (on the left) traditional bump bonds which are used to interconnect two circuit layers. (middle) A bulk-silicon-based through wafer via approach being pursued by several research organizations. (right) Lincoln’s approach based on SOI layer transfer. Note the much smaller size and 3-layer integration demonstrated by the MIT-LL approach.
Lincoln’s approach :
-- wafer scale
- extendable to multiple layers
(This slide previously cleared for ISSCC slide #4)
10 mm
10 mm
Photo Courtesy of RTI
Bump Bond used to
flip-chip interconnect
two circuit layers
Two-layer stack using Lincoln’s SOI-based vias
Two-layer stack with insulated vias through thinned bulk Si

17. Comparison CMOS vs. CCD for Astronomy
Property
CCD
Hybrid CMOS
Resolution
> 4k x 4k
2k x 2k in use, 4k x 4k demonstrated
Pixel pitch
10 – 20 µm
18 – 40 µm, < 10 µm demonstrated
Typ. wavelength coverage
400 – 1000 nm
400 – 1000 nm with Si PIN
400 – 5000 nm with InSb or HgCdTe
Noise
Few electrons
Few electrons with multiple sampling
Shutter
Mechanical
Electronic, rolling shutter
Power Consumption
High
Typ. 10x lower than CCD
Radiation
Sensitive
Much less susceptible to radiation
Control Electronics
High voltage clocks, at least 2 chips needed
Low voltage only,
can be integrated into single chip
Special Modes
Orthogonal Transfer,
Binning,
Adaptive Optics
Windowing, Guide Mode,
Random Access, Reference Pixels,
Large dynamic range (up the ramp)
Silicon PIN hybrid detectors have become a serious alternative to CCDs providing a number of significant advantages, specifically for large mosaic focal plane arrays.