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POLITECNICO DI BARI Front-end for Silicon Photomultiplier (SiPM)

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Presentation on theme: "POLITECNICO DI BARI Front-end for Silicon Photomultiplier (SiPM)"— Presentation transcript:

1 POLITECNICO DI BARI Front-end for Silicon Photomultiplier (SiPM)


3 Politecnico di Bari R q : quenching resistor (hundreds of k ) C d : photodiode capacitance (few tens of fF) C q : parasitic capacitance in parallel to R q (smaller than C d ) I AV : current source modelling the total charge delivered by a microcell during the avalanche C g : parasitic capacitance due to the routing of the bias voltage to the N microcells, realized with a metal grid. Example: metal-substrate unit area capacitance 0.03 fF/mm2 metal grid = 35% of the total detector area = 1mm2 Avalanche time constants much faster than those introduced by the circuit: I AV can be approximated as a short pulse containing the total amount of charge delivered by the firing microcell Q= V(C d +C q ), with V=V BIAS -V BR Cg 10pF, without considering the fringe parasitics Electrical model of a SiPM

4 Politecnico di Bari Experimental validation of the model Two different amplifiers have been used to read-out the FBK-irst SiPM a) Transimpedance amplifier BW=80MHz Rs=110 Gain=2.7k b) Voltage amplifier BW=360MHz Rs=50 Gain=140 The model extracted according to the procedure described above has been used in the SPICE simulations The fitting between simulations and measurements is quite good

5 Politecnico di Bari RSRS SiPM Vbias ISIS k I S = I OUT Charge sensitive amplifierVoltage amplifierCurrent amplifier - + SiPM Vbias CFCF V OUT + - RSRS SiPM Vbias V OUT A I-V conversion is realized by means of R S The value of R S affects the gain and the signal waveform V OUT must be integrated to extract the charge information: thus a further V-I conversion is needed R S is the (small) input impedance of the current buffer The output current can be easily replicated (by means of current mirrors) and further processed (e.g. integrated) The circuit is inherently fast Less problems of dynamic range The charge Q delivered by the detector is collected on C F If the maximum V OUT is 3V and Q is 50pC (about 300 SiPM microcells), C F must be 16.7pF Perspective limitations in dynamic range, die area, power consumption Front-end electronics: different approaches

6 Politecnico di Bari Main simulated specs Small signal bandwidth: 250MHz Input resistance: 17 Total current consumption: 800uA Linearity dynamic range: about 50pC Rise time of the output waveform: 400ps 3.3V power supply Vrif variable in the range 1V÷2V 0.35 m standard CMOS technology Common gate configuration (M1) Feedback applied to increase bandwidth and decrease input resistance (M3, M2) SiPM bias (and gain) fine tuning possible by varying Vrif The CMOS current buffer

7 Politecnico di Bari 7V Experimental setup: blue LED light source Picture of the setup Single dark pulse measurement (V br =-30.5V; V bias =-32.5V) The circuit has been coupled to a SiPM realized by FBK-Irst Blue Led I out 50Ω Pulse Generator Current Buffer Voltage Amplifier BNC SiPM R IV

8 Politecnico di Bari Dark pulse measurements Charge measurements at V bias = -32.5V Comparison with a very fast discrete voltage amplifier front-end, used as a reference: Average dark pulse charge Integrated current buffer: 143fC Discrete voltage amplifier: 142fC The standard deviation is worse: int 2 disc Blue LED measurements Average number of fired microcells as a function of the input pulse width Charge distribution for a 8.25ns input pulse width (in terms of no. of fired microcells) Comparison with the ref. amplifier : Average no. of fired microcells Current buffer: 39 Ref. amplifier: 38.4 Standard deviation Current buffer: 7.5 Ref. Amplifier: 7.2

9 Politecnico di Bari Architecture of the analog channel Variable gain integrator: Gain: 1V/pC 0.33V/pC (2 bits); f = 200ns; Output voltage range: 0.3V ÷ 2.7V; Current mirror scaling factor 10:1 Current discriminator: Current mirror scaling factor 1:1; Threshold variable from 0 to 40µA (about 50 V BIAS =-31.5V); Baseline holder : Baseline value Vbl = 300mV Very slow time constant; Non-linearities added to prevent baseline shifts at increasing event rates

10 Politecnico di Bari Experimental setup: LED light source Lemo Blue Led SiPM Vbias 50Ω Lemo Pulse Generator Voltage Buffer Logic Buffer Chip Ch_in Ch_out Disc SiPM A51 ( FBK – IRST ) Blue Led HSMB-C150 Typical output waveforms (Vbias=31.5V)

11 Politecnico di Bari Charge measurements (blue LED light source) Ouput voltage vs pulse width for different gain settings From the previous characterization measurements we have: For pulse width = 9ns, n=115 fired microcells If Vbias = 31.5 V, the total injected charge is Q T = Q µcell (31.5V)*n = 6.9pC If Vbias = 32.5 V, the total injected charge is Q T = Q µcell (32.5V)*n = 17.3pC Vbias31.5V32.5V Q T /(M*C f )690mV1.73V V peak -V bl 670mV1.76V Measurement are in good agreement with the expected results

12 Politecnico di Bari OTA _ + Integrator output out I BIAS V DISC C hold =2pF reset V DD M1M1 M2M2 MRMR Design of the 8 channel ASIC: the Peak Detector (PD) It is based on a P-MOS current mirror as a rectifying element I BIAS added to improve the speed of operation, especially for small signals

13 Politecnico di Bari Cur_disc M0M0 M1M1 M7M7 trig_0 trig_1 trig_7 Vdd Vbias I bias I0I0 I1I1 I2I2 I thresh C bus F_or I thresh = I 2 -(I 0 -I 1 ) M NBUF M PBUF Fast-OR circuit operating in current mode, to improve the speed of operation Current buffer to reduce the input impedence Current discriminator with fixed treshold Design of the 8 channel ASIC: the fast-OR

14 Architecture of the test chip

15 Politecnico di Bari Design of the 8 channel ASIC: Layout

16 Politecnico di Bari Read-out procedure for the test chip A)An event activates the SRQ bus (by default at Hi-Z) B)FPGA gives a time-stamp to the event and takes control of the SRQ bus during the read-out procedure C)SRQ, in its active state, is used to freeze the content of the trigger registers (no more trigger are accepted) D)FPGA waits the time needed by the PDs to reach the peak and sends the CLOCK signal to the ASICs F)The read-out logic starts the A/D conversions and sends the results to FPGA on the DATA_i pad G)When all the conversions have been completed, FPGA releases the SRQ bus and sends a RESET signal SRQ CHIP DATA CLOCK FPGA DATA_0 CLOCK SRQ RESET Package SMD

17 Politecnico di Bari Jitter measurements on fast-OR signal Canale colpito Valore medio del ritardo Deviazione standard ns50 ps ns53 ps ns49 ps ns49 ps ns48 ps ns49 ps ns49 ps ns48 ps Coppia canali Valore medio del ritardo Deviazione standard ns47.26 ps ns50.5 ps ns48.6 ps ns49.7 ps ns49 ps ns50.3 ps ns50 ps ns50.5 ps ns50 ps Misure di jitter in presenza di un solo canale soprasoglia Misure di jitter in presenza di due canali soprasoglia

18 Design of the 32 channel ASIC: Logic Readout config_reg DAC Vrif DAC I_th MUX_reg Trig. reg. MUX ADC_1 Logic Readout srq_pad Vrif F_or reset_pad ck_pad rw_pad gain EOC pd_out_0 pd_out_1 pd_out_31 trig_0 trig_1 trig_31 I_th data ADC_2 SPI interface DEMUX DEMUX_reg ex_ADC MUX ADC/Clock Manager cK_ADC MUX_reg SDI_pad SDO_pad SS coincidence_pad Politecnico di Bari

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