1. Status of MicroTCA LLRF Development Zheqiao Geng On behalf of the LLRF AIP team 6/4/2012

2. 2015-8-7Zheqiao Geng, MicroTCA LLRF2 Outline History of LLRF at SLAC MicroTCA Based LLRF System Overview FPGA Firmware Design EPICS Software Design Applications for Operation System Tests Summary

3. 2015-8-7Zheqiao Geng, MicroTCA LLRF3 History of LLRF at SLAC

4. 2015-8-7Zheqiao Geng, MicroTCA LLRF4 SLAC Linac

5. 2015-8-7Zheqiao Geng, MicroTCA LLRF5 Existing RF System of Linac 30 Sectors (LCLS uses the last 10 of them) Each sector contains of 8 klystrons and 1 sub-booster Every RF station has 2 racks for controls

6. WG & Cable Penetration to Tunnel

7. PAD Chassis Measures RF Phase and Amplitude MKSU Chassis Interlock and Control for Klystron SLED Support Systems PIOP CAMAC Module Controls IPA, PAD, and MKSU. Interface to control system Existing Linac Klystron Station RF Control, Monitoring, and Interlocking System IPA Chassis Controls RF Phase and Amplitude Existing Controls Racks 7

8. Controls Upgrade Implementation PDU TimingPIOPs (4) 12-01-108

9. Controls Upgrade Implementation12-01-109

10. 2015-8-7Zheqiao Geng, MicroTCA LLRF10 LLRF for LCLS Several critical RF stations were upgraded for LCLS with newly designed Phase and Amplitude Detector (PAD), Phase and Amplitude Controller (PAC) and VME running EPICS The old IPA, MKSU and CAMAC system is kept (not shown in the diagram below)

11. 2015-8-7Zheqiao Geng, MicroTCA LLRF11 LLRF for LCLS (cont.) PAD : Custom chassis with 4 channels of down mixers and ADCs PAC : Custom chassis with a DAC board and an I/Q modulator

12. 2015-8-7Zheqiao Geng, MicroTCA LLRF12 Some Limitations of PAD/PAC A feedback control loop has to follow the chain of PAD-VME-PAC connected with Ethernet, the real-time performance is limited. It is not possible to do intra-pulse control (pulse width ~ 3 µs) Computation power of the Coldfire MCU used in PAD/PAC chassis is quite limited. One more Channel Access client connected to the EPICS software in the Coldfire MCU can significantly degrade its real-time performance One PAD chassis (2U or 3U) only contains 4 ADC channels. The density is too low to efficiently use the rack space Custom designed chassis is difficult to maintain The MicroTCA based LLRF system presented in this talk tends to upgrade the PAD/PAC system to be more compact, flexible, maintainable and reliable…

13. 2015-8-7Zheqiao Geng, MicroTCA LLRF13 Overview of the MicroTCA Based LLRF System

14. 2015-8-7Zheqiao Geng, MicroTCA LLRF14 PAD/PAC LLRF VS MicroTCA LLRF

15. 2015-8-7Zheqiao Geng, MicroTCA LLRF15 RF Support Chassis

16. 2015-8-7Zheqiao Geng, MicroTCA LLRF16 MicroTCA Crate

17. 2015-8-7Zheqiao Geng, MicroTCA LLRF17 AMC Carrier + PMC EVR

18. 2015-8-7Zheqiao Geng, MicroTCA LLRF18 AMC ADC Board – SIS8300 Struck SIS8300 Board 4 lane PCI Express 10 Channels 125 MS/s 16-bit ADC Two 16-bit DACs for Fast Feedback Implementation Twin SFP Card Cage for High Speed System Interconnects Virtex 5 FPGA The board is equivalent to the digital parts of 2.5 PADs + 1 PAC!

19. 2015-8-7Zheqiao Geng, MicroTCA LLRF19 Summary of Hardware Architecture Compared to the PAD/PAC chassis, the MicroTCA based LLRF system uses commercial digital boards to reduce the R&D time MicroTCA system has much higher density of ADC/DAC channels. The system is more compact Compared to the PAD/PAC chassis, the digital hardware of the new design is installed in the MicroTCA crate. The boards are hot-swappable and easy to maintain To be improved (nice to have): An AMC EVR board will be introduced to route trigger signals via the backplane. ADC boards will take triggers from backplane to remove the trigger cables The RTM with S-band down mixers from DESY will be evaluated. The system can be more compact by moving the down mixers and up converter to the RTM board from the RF support chassis The klystron beam voltage conditioner board will be improved to directly measure the flattop of the voltage pulse by adding offset to the klystron beam voltage signal

20. 2015-8-7Zheqiao Geng, MicroTCA LLRF20 FPGA Firmware (for SIS8300) Design

21. 2015-8-7Zheqiao Geng, MicroTCA LLRF21 Major Requirements to the Firmware Intra-pulse phase feedback control Provide 64K sampling buffer for each ADC channel (10 channels) DAC can be used as an arbitrary waveform generator Exception detection and handling

22. 2015-8-7Zheqiao Geng, MicroTCA LLRF22 Overview of the Firmware

23. 2015-8-7Zheqiao Geng, MicroTCA LLRF23 Algorithm for Intra-pulse Phase Control Align the vector along the I axis so that Q components will be proportional to the phase jitter Phase error is estimated at the first part of the RF pulse and the correction is applied at the second part of the RF pulse (latency < 1 µs) Demodulation I Q Vector Rotation I Q Correction I Q

24. 2015-8-7Zheqiao Geng, MicroTCA LLRF24 ADC Data Acquisition Allow up to 64K point data acquisition for ADC SNR calculation 64 K samples from ADC2 Spectrum by FFT (SNR = 77 dBFS)

25. 2015-8-7Zheqiao Geng, MicroTCA LLRF25 DAC Waveform Generation Specify arbitrary I/Q waveforms in two 2048-point buffers for two DACs Allow CW output regardless of trigger Example: In-phase and Quadrature waveforms for single side band modulation Waveforms Generated by 2048- point Buffers (triggered output) Waveforms Generated by 2048- point Buffers (CW output)

26. 2015-8-7Zheqiao Geng, MicroTCA LLRF26 RF System Simulator Simulate the klystron output and SLED output The simulator can be used to test most of the functions in the lab Input to the RF System Simulator Simulated Klystron Output (25.5 MHz IF) Simulated SLED Output (25.5 MHz IF)

27. 2015-8-7Zheqiao Geng, MicroTCA LLRF27 EDM Panel for Firmware Control

28. 2015-8-7Zheqiao Geng, MicroTCA LLRF28 Summary of Firmware Design MicroTCA based LLRF system connects ADCs and DACs to the same FPGA to enable the intra-pulse control The powerful FPGA is used to implement most of the complex real-time functions to relax the CPU load. 360 Hz operation or multi-bunches operation can be well supported PCI Express links the FPGA and CPU to enable faster data transfer which improves the data acquisition capability To be improved (basic): The firmware will be extended to be general and configurable for all RF stations (CW control, Laser control, RF Gun control, X-band and S-band klystron control) Intra-pulse phase feedback will be upgraded for both amplitude and phase control. I/Q control scheme will be used To be Improved (nice to have): Improve the intra-pulse control refer to the klystron high voltage jitters if they have stronger correlations Improve the up conversion algorithm to reduce the non-linearity of the phase and amplitude actuation

29. 2015-8-7Zheqiao Geng, MicroTCA LLRF29 EPICS Software Design

30. 2015-8-7Zheqiao Geng, MicroTCA LLRF30 Software Architecture

31. 2015-8-7Zheqiao Geng, MicroTCA LLRF31 EDM Panels – RF Station Top

32. 2015-8-7Zheqiao Geng, MicroTCA LLRF32 EDM Panels – Pulse-pulse Phase Control

33. 2015-8-7Zheqiao Geng, MicroTCA LLRF33 EDM Panels – LLRF Timing Settings

34. 2015-8-7Zheqiao Geng, MicroTCA LLRF34 EDM Panels – RF Synchronous DAQ Save all phase and amplitude values of the RF signals for the same RF pulse synchronously up to 65536 pulses Save all waveforms for the same RF pulse synchronously up to 2048 pulses

35. 2015-8-7Zheqiao Geng, MicroTCA LLRF35 EDM Panels – RF Waveforms

36. 2015-8-7Zheqiao Geng, MicroTCA LLRF36 Summary of Software Design PAD/PAC based LLRF system has software pieces in PAD CPU, PAC CPU and VME CPU, they communicate with each other via UDP. The architecture is complex and difficult to maintain. The computation power of these CPUs are quite limited MicroTCA based LLRF system has one much more powerful CPU. Real-time Linux OS will be used and it is much more flexible to be adapted to the newest multi-core CPUs MicroTCA software is compiled to a single IOC process so the number of maintenance points is reduced Data and waveforms can be saved at 120 Hz for diagnostics. Later this function can be synchronized by Timing System for all RF stations so that the behavior of the entire machine can be analyzed within one RF pulse Software architecture is more modular and understandable To be improved (basic): Software should be improved to fit the extended firmware MicroTCA infrastructure (such as software development tools, EPICS base, boot up tools) needs to be improved. This topic will be covered by Charlie Xu’s talk

37. 2015-8-7Zheqiao Geng, MicroTCA LLRF37 LLRF Applications

38. 2015-8-7Zheqiao Geng, MicroTCA LLRF38 LLRF Applications Examples of Applications for A RF Station Measure the klystron energy no-load Measure klystron saturation curve Measure the beam phase with beam induced signal Calibration of the imbalance of the I/Q modulator and DAC offset Loop phase correction for intra-pulse feedback control Intra-pulse feedback gain optimization DAC waveform generation for single side band up-conversion Set klystron mode to ACC or standby Most of the applications already exist for the old RF stations. The new LLRF software will inherit the existing algorithms and codes

39. 2015-8-7Zheqiao Geng, MicroTCA LLRF39 System Test

40. 2015-8-7Zheqiao Geng, MicroTCA LLRF40 ADC Noise Measurement ADC0ADC1ADC2ADC3ADC4ADC5ADC6ADC7ADC8ADC9 At Lab77.478.678.279.478.278.877.078.879.179.2 At 28-276.176.7 77.276.577.476.777.677.4 Signal to Noise Ratio (dBFS) ADC0ADC1ADC2ADC3ADC4ADC5ADC6ADC7ADC8ADC9 ADC0088.98797.395.2111.6106.2112.2103.5112.3 ADC182.7087.198.597105108.5112.9104.6108.9 ADC282.384.1086.18798.696.8113104.4112.2 ADC395.894.781.2097.198.598.9109.8103.9111.5 ADC491.593.483.897.7085.585.198.6 109.9 ADC599.2101.195.194.981.3092.5101.1100.4111.8 ADC6100.2101.494.393.68188.5087.288.9107.3 ADC798.9102.4103.5102.494.997.881.7084.7109.7 ADC8100.5102.1105.4104.69694.784.381.1095.2 ADC999.3102.3104.8 100.9106.4106.5101.592.40 Crosstalk Matrix (dB)

41. 2015-8-7Zheqiao Geng, MicroTCA LLRF41 Phase and Amplitude Measurement Noise 119 MHz clock jitter: 257 fs integrated from 10 Hz to 40 MHz With a -1dBFS 25.5 MHz IF input and 257 fs clock jitter, the measurement noises (in full bandwidth of ADC) are expected to be: Phase : 0.01 deg RMS Amplitude: 0.02 % RMS Considering the bandwidth of the RF system in the view of the beam (~1.2 MHz), the measurement noises will meet the LCLS-II requirements (0.07 deg RMS phase jitter and 0.06 % RMS amplitude jitter for the most critical RF station of L1S)

42. 2015-8-7Zheqiao Geng, MicroTCA LLRF42 Installation at LI28-2 SSSB RF Support Chassis MicroTCA Crate MKSUII

43. 2015-8-7Zheqiao Geng, MicroTCA LLRF43 System Test at LCLS Linac (LI28-2) - RF Signal Measurement

44. 2015-8-7Zheqiao Geng, MicroTCA LLRF44 RF Reference Signal

45. 2015-8-7Zheqiao Geng, MicroTCA LLRF45 I/Q Modulator Output Signal

46. 2015-8-7Zheqiao Geng, MicroTCA LLRF46 Klystron Drive Signal

47. 2015-8-7Zheqiao Geng, MicroTCA LLRF47 Klystron Output Signal

48. 2015-8-7Zheqiao Geng, MicroTCA LLRF48 SLED Output Signal

49. 2015-8-7Zheqiao Geng, MicroTCA LLRF49 System Test at LCLS Linac (LI28-2) - Reference Tracking

50. 2015-8-7Zheqiao Geng, MicroTCA LLRF50 Reference Tracking Subtract the phase of the reference signal from other RF signal phases Remove the common mode error caused by the RF detectors experiencing the same temperature fluctuations Remove the phase jump caused by the clock re-synchronization Reference Phase Klystron Output Phase SLED Output Phase

51. 2015-8-7Zheqiao Geng, MicroTCA LLRF51 System Test at LCLS Linac (LI28-2) - Pulse-pulse Feedback

52. 2015-8-7Zheqiao Geng, MicroTCA LLRF52 Long Term Stability with Feedback 2-hour phase measurement

53. 2015-8-7Zheqiao Geng, MicroTCA LLRF53 System Test at LCLS Linac (LI28-2) - Intra-pulse Feedback

54. 2015-8-7Zheqiao Geng, MicroTCA LLRF54 Intra-pulse Feedback Phase error is estimated at the first part of the RF pulse and the correction is applied at the second part of the RF pulse Loop delay should < 1 µs Phase jitter of different parts of the RF pulse should be correlated The entire loop delay is ~ 600 ns, quite promising for intra- pulse feedback.

55. 2015-8-7Zheqiao Geng, MicroTCA LLRF55 Phase Jitter Correlation Correlation coefficient of the phase jitter between different parts of the RF pulse ~ 0.3-0.4

56. 2015-8-7Zheqiao Geng, MicroTCA LLRF56 Intra-pulse Feedback Gain Sweeping Phase Jitter / deg Feedback Gain Effects of the intra-pulse feedback on the beam can only be tested at the sensitive RF stations (like L1S) Correlation of the phase jitters of different parts of the RF pulse is not so strong How about the correlation between phase jitter and the klystron high voltage?

57. 2015-8-7Zheqiao Geng, MicroTCA LLRF57 System Test at LCLS Linac (LI28-2) - Intra-pulse phase slope compensation

58. 2015-8-7Zheqiao Geng, MicroTCA LLRF58 Motivations At rising edge of the klystron signal, the phase changes > 100 deg, which will lower the efficiency to fill the SLED cavities Klystron signal after PSK has a phase change > 60 degree, which will lower the integrated E field seen by the beam Idea: Remove the phase slope with feed forward to possibly increase the energy gain from the klystron

59. 2015-8-7Zheqiao Geng, MicroTCA LLRF59 Phase Slope Compensation with Feed Forward

60. 2015-8-7Zheqiao Geng, MicroTCA LLRF60 SLED Amplitude with Feed Forward Iterations Amplitude of SLED output can be increased by ~ 3 % Note: There is still 10 degree phase change at the SLED output pulse during the part that interacts with the beam! The MicroTCA based LLRF system provides a very powerful platform to implement the new ideas from physicists

61. 2015-8-7Zheqiao Geng, MicroTCA LLRF61 System Test at LCLS Linac (LI28-2) - Phasing the klystron

62. 2015-8-7Zheqiao Geng, MicroTCA LLRF62 Phasing the Klystron with Matlab Need further measurement to clarify if we can really increase the energy gain or not! Without phase feed forward controlWith 50 iterations of phase feed forward control

63. 2015-8-7Zheqiao Geng, MicroTCA LLRF63 More Tests Need to be Done Intra-pulse I/Q control need to be tested at critical RF stations like L1S before the first bunch compressor. The effects of the intra-pulse control can be examined by monitoring the beam stability Measurement of beam induced signal need to be done at LI28-2. To do this test, the klystron need to be in standby state Correlation between RF amplitude/phase jitters and klystron high voltage jitter need to be tested. This will tell us if we can use the klystron high voltage jitter for intra-pulse feedback. As mentioned before, a new klystron beam voltage conditioner board need to be designed More tests need to be done to check if the intra-pulse phase slope compensation can increase the energy gain or not

64. 2015-8-7Zheqiao Geng, MicroTCA LLRF64 Summary

65. 2015-8-7Zheqiao Geng, MicroTCA LLRF65 Summary of MicroTCA System MicroTCA introduces intra-pulse control to reduce fast jitters MicroTCA system uses PCI express for faster data acquisition which enables to save the RF waveforms at 120 Hz or even at 360 Hz MicroTCA system uses more powerful FPGA and CPU which enables to upgrade the system for 360 Hz or multi-bunch operation without changing the hardware MicroTCA system contains more ADC channels in a single board which enables to implement the reference tracking to remove the phase jump problem in digital I/Q demodulation algorithm The PAD/PAC system uses Coldfire MCU which is a bottleneck for real-time performance. The PAD-VME-PAC chain is connected with Ethernet and it is not possible to perform intra-pulse control. 120 Hz waveform saving is poorly supported as well

66. 2015-8-7Zheqiao Geng, MicroTCA LLRF66 Summary of MicroTCA System (cont’d) MicroTCA has better upgradability: overhead in data transfer speed (PCI Express) and computation power (FPGA + multi-core CPU) MicroTCA has better maintainability: hot-swappable – reducing repair time – more availability MicroTCA has better reliability – simpler and more compact system structure; redundant MCH and power supply MicroTCA has better platform management – IPMI MicroTCA is a new platform which needs more development efforts Cost is relatively high due to small market

67. 2015-8-7Zheqiao Geng, MicroTCA LLRF67 Thank you!

68. 2015-8-7Zheqiao Geng, MicroTCA LLRF68 Backup Slides

69. 2015-8-7Zheqiao Geng, MicroTCA LLRF69 Phase and Amplitude Actuation Noise I/Q modulator Input Jitters: Phase 0.083 deg RMS, Amplitude 0.01% I/Q modulator Output Jitters: Phase 0.074 deg RMS, Amplitude 0.03% The phase and amplitude actuation does not introduce extra noise (or at least neglectable)