1. Ultra-Low Power | High Integration | Easy-to-Use
MSP430
Ultra-Low Power | High Integration | Easy-to-Use
“How To” Series: JTAG
2011

2. Introduction Purpose Objectives
Provide a brief but informative technical overview in “HOW-TO” use the MSP430 JTAG interface
Objectives
Discuss What is JTAG?
Discuss how JTAG applies to MSP430 devices
Discuss Interface capabilities
Discuss Design considerations
Hello, welcome to the MSP430 “How to” use JTAG interface product training module. This session is intended to provide a brief but informative technical overview in “HOW-TO” use the MSP430 JTAG interface; both in terms of understanding its purpose as well as how to best leverage this interface in your specific MSP430 HW design.
Over the next few slides we will be looking into JTAG, how it is used in MSP430 & its capabilities, and considerations that you should keep in mind when designing with MSP430.

3. What is JTAG? “JTAG”- Joint Test Action Group
Originally and industry group formed to develop methodology for testing circuit board assemblies after manufacture
Industry standard IEEE Std
Synonymous with
Debugging, Memory programming and/or Boundary scan testing
4 or 5 wire physical interface
TDI (Test Data In), TDO (Test Data Out), TCK (Test Clock), TMS (Test Mode Select), TRST (Test Reset) optional
No standard connector or adapter HW
Vendor-specific, often with extensions that use the JTAG interface
First, let’s take a look at JTAG and what it is. JTAG stands for “Joint Test Action Group” and was originally crafted as an entity that developed test methods for printed circuit boards. The guidelines and implementation was adopted as an IEEE industry standard in 1990 and has come to represent the interface by which an embedded design can be programmed, debugged and tested. Physically, JTAG is a 4 wire interface (5-wire if considering the optional reset pin) consisting of data I/O, clock and mode signals. While the pinout is standard, there is no defined HW interface standard. The physical connector used by suppliers of JTAG-enabled products are free to identify a pinning that suits their specific portfolio and tool chain requirements.
Reference: Wikipedia

4. How JTAG applies to MSP430 devices
All MSP430 devices are debugged and primarily programmed using JTAG
Standard 4-wire JTAG
Custom 2-wire “SBW” JTAG (supported on select MSP430 devices)
MSP430 uses a 2x7 14-pin header for JTAG connectivity
Reduced pin headers used on some eZ430 HW for SBW-only
Note Boundary Scan is not supported on MSP430 devices today
In-system & BSL are options for memory programming, but only a JTAG interface can be used to debug
JTAG can be disabled to protect SW IP
Now that we have defined what JTAG is, lets dive into what JTAG more specifically means for the MSP430 family. MSP430 JTAG is by definition the 4-wire JTAG interface described earlier: TDO, TDI, TCK & TMS. It is present on all MSP430 catalog devices and is the fundamental interface by which every MSP430 can be programmed as well as debugged. The physical interface is defined as a 2x7 14-pin connector and is used on almost all MSP430 development boards and programmers. In addition to the standard 4-wire JTAG interface, some select MSP430 devices also support a 2-wire TI-proprietary JTAG interface called Spy-Bi-Wire, or “SBW” for short. Simply put, the TI SBW interface time division multiplexes the TDI, TDO & TMS signals along one data connection and TCK is retained as the second connection for clock. Given the implementation, SBW is a bit slower than standard JTAG but makes connecting to the MSP430 easier by cutting required connections by half. Keep in mind that while there are other methods of programming an MSP430 such as bootstrap loader or a custom interface leveraging MSP430’s flexible in-system programming capabilities, JTAG is the only method of debugging an MSP430 MCU. Lastly, an element of JTAG: Boundary scan which can be used to do signal chain I/O testing in multi-IC designs, is not supported today on the MSP430 portfolio. This has been excluded in order to avoid increased silicon costs and more importantly, avoid increased active and standby currents required when implementing boundary scan. This should not create any issues for developers but should be considered up front in systems where designer’s may have been typically leveraging boundary scan on other embedded processors.

5. Interface capabilities: 4-Wire
All MSP430’s support 4-wire mode
A RST connection to the JTAG header is not required on devices that DO NOT support SBW (e.g. 100pin ‘1xx)
TEST must be connected when present the device
General Connections
(see Hardware Tool’s User’s Guide and device-specific datasheets for more information)
MSP430 4-Wire JTAG Signal Implementation Overview
Devices
TEST Pin
4-Wire
20-and 28-pin MSP430F1xx devices*
YES
64-, 80-, and 100-pin MSP430F1xx/4xx devices * NO
MSP430F21x1 family *
14-, 20-, 28-, and 38-pin MSP430F2xx devices
64-, 80-, and 100-pin MSP430F2xx devices *
14-, 16-, 20-, 28-, and 32-pin MSP430G2xx devices
MSP430F5xx/6xx devices
Let’s take a look at the specifics of the MSP430 JTAG interface, starting with the standard 4-wire implementation. The figure shown is from the MSP430 Hardware Tools Users Guide available on TI.com. There you can find additional information not shown here as well as details regarding our other MSP430 catalog tools and programmers with schematics provided. Shown in the figure is the standard interface via 4-wire JTAG to any MSP430. This is found as such in our tools and development boards as well as intended for use by developers designing custom hardware for the MSP430.
Required connections are TDO, TDI, TCK, TMS and GND. When using MSP430 devices that also support SBW, RST is also required (we will cover SBW details in the next slide). The TEST signal is also required IF the given MSP430 device in-use comes equipped with the TEST pin. MSP430 devices that typically make use of TEST are those that have shared pins with JTAG as well as application functionality (such as a UART, timer I/O or other GPIO functions). The TEST signal is used to enable JTAG on those shared pins as well as providing a pin interface to permanently disable the JTAG interface on devices that implement a physical JTAG fuse (such as the 1xx, 2xx and 4xx families). Customers desiring to protect SW IP after programming can disable the device using this fuse and the TEST pin connection. Vcc is not strictly required but highly recommended in order to maintain reliable logic levels during communication. When provided by the host programmer, Vcc can be sourced on pin 2 of the standard MSP430 JTAG header. Alternatively, when the Vcc of the target device is provided on-board and not sourced by the tool, the local Vcc can be provided on pin 4. When used with standard TI MSP430 programmers, this voltage is used as a reference for level shifting the JTAG connections providing proper CMOS logic level transitions during communication.
The table shown indicates device and device sub families that require a TEST pin connection in addition to the 4-wire JTAG. Remember that any devices supporting SBW also carry slightly different pin naming as well. For more details on the SBW implementation, lets take a look at the next slide…
Pin Naming for SBW-capable devices:
RST = RST/SBWTCK
TEST = TEST/SBWTDIO
* These devices do not support the SBW option

6. Interface capabilities: 2-Wire SBW
When physical fuse blow IS needed (e.g. 2xx devices):
Header connection of TEST/VPP required
R2 is required to protect the TCK pin
When physical fuse blow IS NOT needed (e.g. all 5xx/6xx devices):
Omit header connection to TEST/VPP
R2 = 0 Ohm
C2 must not exceed 2.2nF to assure reliable SBW communication
General Connections
(see Hardware Tool’s User’s Guide and device-specific datasheets for more information)
MSP430 2-Wire JTAG Signal Implementation Overview
Devices
TEST Pin
2-Wire SBW
20-and 28-pin MSP430F1xx devices *
YES NO
64-, 80-, and 100-pin MSP430F1xx/4xx devices *
MSP430F21x1 family *
14-, 20-, 28-, and 38-pin MSP430F2xx devices
64-, 80-, and 100-pin MSP430F2xx devices *
14-, 16-, 20-, 28-, and 32-pin MSP430G2xx devices
MSP430F5xx/6xx devices
As discussed previously for 4-wire, here are the specifics to MSP430 SBW support. As you can see, the connections required reduce simplifying the physical design requirements to interface to the MSP430. The connections consist of the clock, SBWTCK as well as the bidirectional data line, SBWTDIO. These pins of the given MSP430 are to be connected to pin 1, TDO/TDI, and pin 7, TCK, respectively in order for the SBW interface to properly function with a MSP430 JTAG programmer. GND and VCC connections apply as described earlier for the 4-wire implementation and are identical. Handing of the TEST pin at the programmer side, pin 8 on the header, is only required in the case that a physical JTAG fuse on a given MSP430 target device needs to be blown post-programming. If this is the case, it is important to also provide R2 as shown above. This will protect the TCK pin of the programmer from the high fuse blow voltage that is driven onto the TEST/SBWTCK pin during the fuse blow procedure. An additional requirement is regarding capacitance on the RST/SBWTDIO pin. Often, having a small capacitance on this pin is helpful in-design to reduce noisy transitions that can appear, resetting the device during power transients or noisy events such as ESD discharges and PCB-related noise coupling. A typical value is 10nF however must be kept below a maximum of 2.2nF for valid SBW communication. Values exceeding this may degrade the high/low edge transitions to a point that SBW communication is no longer possible. In designs that need a larger capacitor on RST for any reason, it should only be populated AFTER the SBW programming of the target.
Here you can also find a table indicating MSP430 devices and sub families supporting the SBW mode. Support for SBW is found typically on our smaller devices due to the advantages of consuming fewer pins with a minimized application design impact. All newer F5xx and F6xx devices support both 4-wire and 2-wire SBW, independent of physical size or pin count.
* These devices do not support the SBW option

7. Design considerations
JTAG pins are often multiplexed in the device
Consider using non-JTAG functions in-application carefully to avoid conflicts with JTAG tools & communication signals
Using a larger capacitor on RST in-application is sometimes favorable to help filter noise that might cause unwanted resets
This is acceptable in-application, but limit to 2.2nF for purposes of using JTAG
Keep routing of JTAG/RST/TEST signals as short as possible & isolated from other circuitry
Protects against noise coupling into the application during debug
Helps limit exposure of JTAG/RST pins to unwanted spikes due to noise, ESD, etc.
When one or more JTAG pins are not used, please refer to the device-specific User’s Guide section “Connection of Unused Pins” for guidance
When programming via JTAG, keep in mind 4-wire JTAG is ~3x faster than using SBW
Now lets wrap up by taking a look into a few design considerations valuable for developing customer solutions with MSP430. As mentioned earlier, JTAG pins of the MSP430 is often multiplexed with other GPIO or peripheral functions. This should be considered up front in the design planning and system definition. It is a good practice to use these pins in application as a last resort when equivalent functions exist on other non-JTAG pins. In the case these pins must be used, consider the direction required for JTAG communication and connect accordingly to avoid any logic contention between the host programmer and the system circuitry. This is not a concern when using the SBW interface for MSP430 JTAG.
Also keep in mind the capacitor on the RST pin to avoid overloading, especially during SBW activity.
It is a good practice to be conscious of routing placement of JTAG signals in any design. Not only can these signals generate noise during JTAG access that might interfere with the application, but it is also possible for the application environment to project noise onto the JTAG lines causing errant operation of the device. Most notably, one might see sporadic RST behavior triggered by noise coupling onto the RST pin if noise free PCB design is not considered for the RST line. This is generally only an issue if traces get long, if they are close to noisy circuitry or perhaps are susceptible to ESD strikes.
When JTAG or any MSP430 pin is not used in a design, please consult the device-specific family user’s guide for recommendations & requirements for properly handling these connections. This is typically found in chapter 1 or 2 of the given users guide near the end of the chapter.
And lastly, remember the tradeoffs for choosing 4- or 2-wire JTAG on the MSP430. The 4-wire approach requires more pins but is compatible with ALL MSP430 devices and is the fastest manner in which to program the memory. SBW will provide few physical connections but will be ~1/3 the interface speed vs 4-wire JTAG due to the multiplexing implemented to reduce the pin count.

8. References MSP430 Hardware Tools User's Guide
Describes the hardware of the Texas Instruments MSP-FET430 Flash Emulation Tool, the primary development tool for the MSP430, as well as a broad selection of other MSP430 target boards and development platforms.
MSP430 Programming Via the JTAG Interface
Describes the functions required to erase, program, and verify the memory module of the MSP430 using the JTAG communication port (4-wire & 2-wire “SBW”) for use when developing custom programming solutions; an example implementation is provided.
Your specific MSP430 device’s datasheet & Family User’s Guide
Here are a few links to additional references on the MSP430 JTAG topic. Within these documents you can find additional information to that presented as well as details as to how one can implement their own custom JTAG host for programming a target MSP430 device. And as always, keep in mind the valuable information in the device-specific datasheet and family user’s guide.
Thanks for your time and thanks for your interest in using the Texas Instruments MSP430 microcontroller family.

9. Thank you!