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1 Fabio Vitucci - VIII Workshop PisaTel - December, 6th 2005 - SSSUP TITOLO TESI VIII Workshop PisaTel - December, 6 th 2005 - SSSUP Gruppo RETI di TELECOMUNICAZIONI.

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Presentation on theme: "1 Fabio Vitucci - VIII Workshop PisaTel - December, 6th 2005 - SSSUP TITOLO TESI VIII Workshop PisaTel - December, 6 th 2005 - SSSUP Gruppo RETI di TELECOMUNICAZIONI."— Presentation transcript:

1 1 Fabio Vitucci - VIII Workshop PisaTel - December, 6th 2005 - SSSUP TITOLO TESI VIII Workshop PisaTel - December, 6 th 2005 - SSSUP Gruppo RETI di TELECOMUNICAZIONI Dipartimento di Ingegneria dellInformazione - Università di Pisa Ing. Fabio Vitucci DESIGN AND IMPLEMENTATION OF A MULTI-DIMENSIONAL PACKET CLASSIFIER FOR NETWORK PROCESSORS

2 2 Fabio Vitucci - VIII Workshop PisaTel - December, 6th 2005 - SSSUP Outline Resume of previous activities Implementation of classification module Programming problems Measurements Future works Conclusions

3 3 Fabio Vitucci - VIII Workshop PisaTel - December, 6th 2005 - SSSUP Resume of previous activities/1 Detailed analysis of the Intel® IXP2400 Network Processor and the available board (Radysis ENP-2611) Choice of a proper application to be implemented on NPs: a packet classification Comparative analysis among many research algorithms Source Address Layer 4 Destination Layer 4 Protocol...Rule 11.14.2.21wwwTCP...R1 13.11.23.*gt 1023TCP...R2 112.*.*.*wwwUDP...R3

4 4 Fabio Vitucci - VIII Workshop PisaTel - December, 6th 2005 - SSSUP Resume of previous activities/2 Comparative analysis among many research algorithms AlgorithmWorst case TimeWorst Case Storage Linear SearchO(N) Hierarchical triesO(W D )O(NDW) Set-pruning triesO(W D )O(N D ) Grid-of-triesO(W D-1 )O(NDW) Cross-productingO(DW)O(N D ) Area-Based QuadtreeO(NW)O(W) FIS-treeO((L+1)W)O(LN 1+1/L ) RFCO(D)O(N D ) Bitmap-intersectionO(DW+N/W)O(DN 2 ) HiCutsO(D)O(N D ) Ternary CAMsO(1)O(N) N = number of entries W = maximum number of bit for level D = number of fields to be processed L = number of level of data structure

5 5 Fabio Vitucci - VIII Workshop PisaTel - December, 6th 2005 - SSSUP Multidimensional Multibit Trie Fields: –IP Source Address and IP Destination Address –Layer 4 Source Port and Destination Port –Layer 4 Protocol Type Hierarchical trie: a tree per dimension –Many levels for dimension –A fixed number of bits for level Performance parameters: –Research speed: 5×O(W/K) –Memory accesses: 12 –Storage complexity: 5×O(2 (k-1) ×N×W/K) Resume of previous activities/3 SA Trie DA Trie SP Trie DP Trie PR Trie

6 6 Fabio Vitucci - VIII Workshop PisaTel - December, 6th 2005 - SSSUP Main bound: –Memory consumption –Rules with unspecified fields (e.g. 131.114.*.*) need explosion of all possible rules Modifications: –A level transition in case of wild-cards Less number of nodes Sometimes more memory accesses More complexity Validation tests with a C simulator –Large saving in memory consumption (table in SRAM) –Small increase in instruction store size Resume of previous activities/4

7 7 Fabio Vitucci - VIII Workshop PisaTel - December, 6th 2005 - SSSUP Implementation of module/1 IPv4 Forwarder Intel

8 8 Fabio Vitucci - VIII Workshop PisaTel - December, 6th 2005 - SSSUP Implementation of module/1 IPv4 Forwarder Intel

9 9 Fabio Vitucci - VIII Workshop PisaTel - December, 6th 2005 - SSSUP Functions of XScale (implemented in C language): –Receiving classification rules –Building multidimensional trie according to received rules to calculate the number of nodes per level and SRAM addresses –Rebuilding multidimensional trie to put data in SRAM to precalculated addresses Functions of Microengines: –Receiving packets –Retrieving proper fields to packet headers –Finding matching rules using data structure in SRAM –Modifying TOS fields Implementation of module/2

10 10 Fabio Vitucci - VIII Workshop PisaTel - December, 6th 2005 - SSSUP Functions of XScale (implemented in C language): –Receiving classification rules –Building multidimensional trie according to received rules to calculate the number of nodes per level and SRAM addresses –Rebuilding multidimensional trie to put data in SRAM to precalculated addresses Functions of Microengines: –Receiving packets –Retrieving proper fields to packet headers –Finding matching rules using data structure in SRAM –Modifying TOS fields Implementation of module/2

11 11 Fabio Vitucci - VIII Workshop PisaTel - December, 6th 2005 - SSSUP Functions of XScale (implemented in C language): –Receiving classification rules –Building multidimensional trie according to received rules to calculate the number of nodes per level and SRAM addresses –Rebuilding multidimensional trie to put data in SRAM to precalculated addresses Functions of Microengines: –Receiving packets –Retrieving proper fields to packet headers –Finding matching rules using data structure in SRAM –Modifying TOS fields Implementation of module/2

12 12 Fabio Vitucci - VIII Workshop PisaTel - December, 6th 2005 - SSSUP Implementation of module/3 le liste relative alle porte hanno struttura diversa, infatti le regole di classificazione, quasi sempre, contengono intervalli di porte. Inoltre i possibili valori delle porte sono 65536, perciò occorrono 16 bit per esprimerli. Nella seconda LW ci sono i soliti 8 bit che indicizzano il nodo successivo e i rimanenti 24 sono di padding index of node *index of node of 2nd level index of node *value of fieldindex of next node value of fieldindex of next nodevalue of fieldindex of next node index of node *value of fieldindex of next node value of fieldindex of next nodevalue of fieldindex of next node index of node *index of next node minimumvaluemaximumvalue index of node *index of next node minimumvaluemaximumvalue index of node *value of fieldnumber of rule value of fieldnumber of rulevalue of fieldnumber of rule long word SRAM Data Table

13 13 Fabio Vitucci - VIII Workshop PisaTel - December, 6th 2005 - SSSUP Functions of µ-engines (implemented in µ-code assembler): –Receiving packets –Retrieving proper fields to packet headers –Finding matching rules using data structure in SRAM –Modifying TOS fields Number of added cycles: 1600 –50 = memory registers initialization –180 = reading first node –150 × 2 = reading nodes of ports –145 × 7 = reading other nodes –15 = final matching –40 = writing TOS field Implementation of module/4

14 14 Fabio Vitucci - VIII Workshop PisaTel - December, 6th 2005 - SSSUP Programming problems/1 Main problems: –Number of SRAM accesses –Rate of SRAM accesses

15 15 Fabio Vitucci - VIII Workshop PisaTel - December, 6th 2005 - SSSUP We want to reduce the idle time Programming problems/2 Multithreaded Programming running threadcontext swap idle thread idle µe µe control memory access latency time thread 0 thread 1 thread 2 thread 3 thread 4 thread 5 thread 6 thread 7

16 16 Fabio Vitucci - VIII Workshop PisaTel - December, 6th 2005 - SSSUP Programming problems/3 Stalling running thread context swap idle thread idle µe µe control memory access latency time thread 0 thread 1 thread 2 thread 3 time thread 0 thread 1 thread 2 thread 3 Decrease the number of active threads for µ-engine

17 17 Fabio Vitucci - VIII Workshop PisaTel - December, 6th 2005 - SSSUP Programming problems/4 Filling running thread context swap idle thread idle µe µe control memory access latency time thread 0 thread 1 thread 2 thread 3 Consolidate adjacent memory accesses time thread 0 thread 1 thread 2 thread 3

18 18 Fabio Vitucci - VIII Workshop PisaTel - December, 6th 2005 - SSSUP AdTech AX4000 Cross-Compiler (XScale programming) Serial Cable Developers Workbench (Microengines Programming) Measurements/1

19 19 Fabio Vitucci - VIII Workshop PisaTel - December, 6th 2005 - SSSUP Measurements/2 ADTech AX4000

20 20 Fabio Vitucci - VIII Workshop PisaTel - December, 6th 2005 - SSSUP Measurements/3 Max packet rate: 2033000 pkt/s (0 lost packets) Number of supported rules: 10000 Performance indipendent from number of rules A fundamental feature: robustness

21 21 Fabio Vitucci - VIII Workshop PisaTel - December, 6th 2005 - SSSUP Measurements/4 Packet delay 35 μsec 100 μsec 1130 μsec

22 22 Fabio Vitucci - VIII Workshop PisaTel - December, 6th 2005 - SSSUP Future Works: Resources/Link Scheduler

23 23 Fabio Vitucci - VIII Workshop PisaTel - December, 6th 2005 - SSSUP Conclusions Analyse the Intel® IXP2400 hardware architecture Select a proper algorithm of packet classification for the IXP2400 Modify the algorithm to capitalize properties of our hardware Build a C Simulator to test the new version Implement XScale functions in C language (building rule table) Implement μ-engines functions in µ-code (finding matching rule) Analyse multithreaded programming Study stalling, filling, and other phenomenons Test working and performance of the classifier Characteristics: 1600 added cycles, 2 Mpkt/s, 10000 rules supported, scalability, robustness in case of congestion

24 24 Fabio Vitucci - VIII Workshop PisaTel - December, 6th 2005 - SSSUP TITOLO TESI Workshop PisaTel - December 6 th 2005 - SSSUP Gruppo RETI di TELECOMUNICAZIONI Dipartimento di Ingegneria dellInformazione - Università di Pisa Ing. Fabio Vitucci DESIGN AND IMPLEMENTATION OF A MULTI-DIMENSIONAL PACKET CLASSIFIER FOR NETWORK PROCESSORS


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