Presentation on theme: "CHEP 2000 Padova Stefano Veneziano 1 The Read-Out Crate in the ATLAS DAQ/EF prototype -1 The Read-Out Crate model The Read-Out Buffer The ROBin ROB performance."— Presentation transcript:
CHEP 2000 Padova Stefano Veneziano 1 The Read-Out Crate in the ATLAS DAQ/EF prototype -1 The Read-Out Crate model The Read-Out Buffer The ROBin ROB performance ROC performance I/O module configurations Conclusions G.Ambrosini, E.Arik, H.P.Beck, S.Cetin, T.Conka, A.Fernandes, D.Francis, Y.Hasegawa, M.Joos, G.Lehmann, J.Lopez, A.Mailov, L.Mapelli, G.Mornacchi, Y.Nagasaka, M.Niculescu, K.Nurdan, J.Petersen, D.Prigent, J.Rochez, L.Tremblet, G.Unel, S.Veneziano, Y.Yasu
CHEP 2000 Padova Stefano Veneziano 3 Read-Out Crate logical model The ROC performs: data collection from many readout links event buffering during LVL2 latency event fragment distribution to Event Builder and LVL2 External I/O channels Internal I/O channels
CHEP 2000 Padova Stefano Veneziano 4 The I/O Module –Each I/O channel, external or internal, has an associated Task –A Task is activated on the occurence of stimuli (messages or event data) –An I/O Module (IOM) is a collection of Tasks associated to an external I/O channel. –All Tasks belonging to an IOM are scheduled within a single process and activated by polling conditions (scheduler) –Event manager API –All components within a ROC communicate via a well defined message passing protocol the baseline implementation of the ROC crate, VMEbus based one Single Board Computer (SBC) per IOM, has evolved to a collapsed solution, where a SBC can handle many external I/O channels.
CHEP 2000 Padova Stefano Veneziano 5 Message passing Based on circular buffers Supported buses: VMEbus, PVIC, PCI, CPU bus, EBIO (TCP/IP) Duplication of R/W pointers ==> no polling on the bus DMA and broadcast used where possible PVIC
CHEP 2000 Padova Stefano Veneziano 6 The MFCC based ROBin The CES MFCC 8441 is a commercially available intelligent PMC –I/O: via user programmable 10k50ev front-end FPGA –Same S/W environment as on SBC (LynxOS 3.0.1) Todays ROB implementation minimizes movement of event fragments over the system bus (need to receive and buffer events of 1 kB at 100 kHz), by using an add-on PMC card (one per Read-Out Link).
CHEP 2000 Padova Stefano Veneziano 7 The ROBin software No device drivers, minimal operating system calls. Single process, scheduler, three tasks to manage one ROL, one internal I/O to ROB-host + firmware.
CHEP 2000 Padova Stefano Veneziano 8 ROBin firmware Firmware on FPGA from VHDL synthesis (40/66 MHz clk): PPC master and slave interface to ROL protocol (S-link) Buffer manager and DMA manager state machines 2 kB data fragment buffering communication to ROBin task via two FIFOs (EM pages stats) PPC ROL (S-link) 603 sdram
CHEP 2000 Padova Stefano Veneziano 9 ROBin interaction ROBin application interacts with ROB- host and event data source (FE-FPGA) The following ROB performance results rely on test programs running on the ROB- host on: Event Location Event Deletion Event Retrieval Scheduler loop ROBin ROB-host PCI
CHEP 2000 Padova Stefano Veneziano 10 Event location Messages over the PPC-PCI- PPC buses No S-Link I/O No broadcast mechanism Best arrangement of events into memory (one event per class) PPCMEM PCI bus RIO PPCMEM MFCC 8441 PMC
CHEP 2000 Padova Stefano Veneziano 11 Event retrieval Messages: single cycles Event data transfer: DMA Transfer bandwidth: ~50 MB/s
CHEP 2000 Padova Stefano Veneziano 12 Event deletion No input of new events, only messages over the system bus. Messages sent in DMA mode Several delete requests packed into one message Delete requests get acknowledged
CHEP 2000 Padova Stefano Veneziano 13 S-Link measurements Rate dominated by event fragment input traffic Max. input rate in best conditions = 145 MB/s (with no messages from ROB-host) (SLIDAS max bandwidth is 160 MB/s) One ROB with one ROBin
CHEP 2000 Padova Stefano Veneziano 14 ROC measurements No S-Link, input emulated All ROB ROBin messages sent in single cycle mode rate dominated by PCI traffic and ultimately by MFCC CPU to ~120 kHz Event data (Messages) Messages + Event data Input fragments + Messages + Event data PPC Not used
CHEP 2000 Padova Stefano Veneziano 15 I/O modules configurations ROC Event Rates event rate (kHz) TRG + EBIF + ROBs TRG/ EBIF + ROBsTRG + EBIF/ ROBs TRG/ EBIF/ROBs One ROB No ROBins TE RRR T EEE RRR T E RRR T EEE RRR TTT To further minimize data movement and message passing, more than one external input can be handled by an IOM TRG ROLs
CHEP 2000 Padova Stefano Veneziano 16 ROC Event Rates with ROBins Max event rate increases when data collection (ROBins to EBIF) is done on the same SBC. Expected ATLAS max ROL bandwitdh 1KBX75(100) kHz 1KB event fragments
CHEP 2000 Padova Stefano Veneziano 17 Conclusions A Read-Out Crate based on the DAQ/-1 design and deployed on COTS components has the functionality required by the ATLAS Trigger/DAQ community Software layering and minimal dependence of the software packages on the operating system adds flexibility without a degradation of performance. It also facilitates porting (move to Motorola/Linux or Intel/Linux) The requirements of many Read-Out Links per Read-Out Buffer have lead to the design of the ROBIN, capable of receiving Event data fragments at the expected Level-1 rates.