1. Pipelining Basics Assembly line concept An instruction is executed in multiple steps Multiple instructions overlap in execution A step in a pipeline is called a pipe stage or pipe segment The time required for a step is called a Machine Cycle Machine cycle in determined by the slowest pipe stage, usually one clock cycle

2. Pipelining Benefits Ideally speaking - In perfectly balanced pipe stages, But in reality: - Stages are not perfectly balanced - There are overheads due to pipelining Two ways to look at the improvement due to pipelining 1.Decrease in CPI 2.Decrease in Clock Cycle Time

3. DLX Implementation without Pipelining Every DLX instruction is executed in at most 5 clock cycles 1.Instruction fetch cycle (IF): IRMem [PC] NPCPC + 4 2.Instruction decode/register fetch cycle (ID): ARegs [IR 6..10 ]; BRegs [IR 11..15 ]; Imm((IR 16 ) 16 ## IR 16..31 )

4. 3.Execution/effective address cycle (EX); The ALU operates on the operands prepared in the prior cycle, performing one of four functions depending on the DLX instruction type. Memory reference: ALUOutputA + Imm; Register - Register ALU instruction: ALUOutputA funcB;

5. Register - immediate ALU instrucion: ALUOutputA op Imm; Branch: ALUOutputNPC + Imm; Cond(A op 0) 4.Memory access/branch completion cycle (MEM): The only DLX instructions active in this cycle are loads, stores, and branches.

6. Memory reference: LMDMem [ALUOutput] or Mem [ALUOutput]B; Branch: if (cond) PCALUOutput else PC NPC 5.Write - back cycle (WB): Register - Register ALU instruction: Regs [IR 16..20 ]ALUOutput; Register - Immediate ALU instruction: Regs [IR 11..15 ]ALUOutput; Load instruction: Regs [IR 11..15 ]LMD;

7. CPI for DLX Branch and store require only 4 cycles Branch frequency is 12% Store frequency is 5% What is CPI? CPI = 4 (.12 +.5) + 5 (.83) = 4.83 Can we improve it?

8. CPI for DLX (Cont’d) ALU instructions are idle during MEM cycle We can complete ALU instruction in 4 cycles Assume ALU instructions frequency is 47% The improved CPI = 4 (012 +.05 +.47) + 5 (.36) = 4.36 Improvement= 4.83 / 4.36 = 1.1

9. Basic Pipeline for DLX Each clock cycle, the hardware initiates a new instruction Each instruction still takes 5 clock cycles to complete During each clock cycle, each stage may be working on a different instruction There may be upto 5 different instructions in the pipeline at a time We need to make sure that we do not cause resource contention

10. Basic pipeline for DLX (cont’d) To allow overlapping execution of multiple instruction Separate instruction and date memories (to avoid conflict in CC4) Register file, needs 2 reads and 1 write in each cycle Increment and store the PC every clock, during IF stage. (raises the issue of how Branches are handled) All operations in a pipe stage must be completed in one clock cycle. Values passed from one stage to the next must be placed in registers, called pipeline registers or pipeline latches.

11. Control Set the Multiplexer (MUX) controls Depends on the instruction in the IR Top ALU input MUX is set by whether instruction in a branch or not (if branch, select ID/EX.NPC) Bottom ALU input MUX is set by whether it is a register - register ALU instruction or not.

12. Performance Issues Pipelining increases instruction throughput - i.e the number of instructions completed per unit time. Pipelining does not reduce the execution time of an individual instruction - it usually increases it slightly (due to pipelining overhead) But increase in throughput means the program runs faster, even though no single instruction runs faster!

13. Pipeline hazards Structural Hazards: due to resource contention Date Hazards: due to data dependency Control Hazards: due to branches, etc Hazards may require the pipeline to stall

14. Speedup from Pipelining

15. Speedup from Pipelining (cont’d)