1. 1 OS & Computer Architecture Modern OS Functionality (brief review) Architecture Basics Hardware Support for OS Features

2. 2 Modern OS Functionality CPU management Concurrency (multiple simultaneous activities) How to achieve it? How to schedule? How to avoid conflict? Memory management Disk management I/O Device Management Advanced: Protection & security support for distributed systems & networks

3. 3 Operating Systems = Governments Infinite RAM, CPU Protect users from each other: safety Fair allocation of resources To each according to his needs Manage resources efficiently

4. 4 Canonical System Hardware CPU: Processor to perform actual computations I/O devices: terminal, disks, video, printer… Memory: data & programs System Bus: Communication channel between above

5. 5 Services & Hardware Support OS ServiceHardware Support ProtectionKernel/User Mode Protected Instructions Base & Limit Registers InterruptsInterrupt Vectors TrapsTrap Instructions I/OInterrupts, Memory-Mapping SynchronizationAtomic Instructions Virtual MemoryTranslation Lookaside Buffers SchedulingTimer

6. 6 Protection OS protects users from each other Users cannot read or write other user’s memory Protects self from users Safe from errant or malicious users Code & data protected

7. 7 Kernel Mode: Privileged Instructions CPU provides “kernel” mode restricted to OS Inaccessible to ordinary users Kernel = core of operating system Privileged instructions & registers: Direct access to I/O Modify page table pointers, TLB Enable & disable interrupts Halt the machine, etc. Indicated by status bit in protected CPU register

8. 8 Protecting Memory: Base and Limit Registers Hardware support to protect memory regions Loaded by OS before starting program CPU checks each reference Instruction & data addresses Ensures reference in range

9. 9 Hardware Support OS ServiceHardware Support ProtectionKernel/User Mode Protected Instructions Base & Limit Registers InterruptsInterrupt Vectors TrapsTrap Instructions I/OInterrupts, Memory-Mapping SynchronizationAtomic Instructions Virtual MemoryTranslation Lookaside Buffers SchedulingTimer

10. 10 Interrupt example I Interrupt: Let CPU work while doing I/O I/O is s..l..o..w for CPU I/O device has own processor When finished, device sends interrupt on bus CPU “handles” interrupt

11. 11 Interrupt example II Interrupt: for fairness Suppose one process is long How can other processes use CPU? Take turns, interrupts when one’s quota finished CPU “handles” interrupt

12. 12 CPU Interrupt Handling Handling interrupts: relatively expensive CPU must: Save hardware state (why?) Registers, program counter Disable interrupts (why?) Invoke via in-memory interrupt vector (like trap vector, soon) Enable interrupts Restore hardware state Continue execution of interrupted process

13. 13 Hardware Support OS ServiceHardware Support ProtectionKernel/User Mode Protected Instructions Base & Limit Registers InterruptsInterrupt Vectors TrapsTrap Instructions I/OInterrupt vectors, Memory- Mapping SynchronizationAtomic Instructions Virtual MemoryTranslation Lookaside Buffers SchedulingTimer

14. 14 Traps Special conditions detected by architecture E.g.: page fault, write to read-only page, overflow, system call On detecting trap, hardware must: Save process state (PC, stack, etc.) Transfer control to trap handler (in OS) CPU indexes trap vector by trap number Jumps to address Restore process state and resume

15. 15 Hardware Support OS ServiceHardware Support ProtectionKernel/User Mode Protected Instructions Base & Limit Registers InterruptsInterrupt Vectors TrapsTrap Instructions I/OInterrupt vectors, Memory- Mapping SynchronizationAtomic Instructions Virtual MemoryTranslation Lookaside Buffers SchedulingTimer

16. 16 Memory-Mapped I/O Direct access to I/O controller through memory Reserve area of memory for communication with device (“DMA”) Video RAM: CPU writes frame buffer Video card displays it Fast and convenient

17. 17 Hardware Support OS ServiceHardware Support ProtectionKernel/User Mode Protected Instructions Base & Limit Registers InterruptsInterrupt Vectors System CallsTrap Instructions I/OInterrupt vectors, Memory- Mapping SynchronizationAtomic Instructions Virtual MemoryTranslation Lookaside Buffers SchedulingTimer

18. 18 Synchronization How can OS synchronize concurrent processes? E.g., multiple threads, processes & interrupts, DMA

19. 19 Synchronization example: bank CPU must provide mechanism for atomicity: Series of instructions that execute as one or not at all Bank account balance: x, deposit $500, withdraw $500, ending balance? 1. R1=x 2. R1= R1+500 3. x=R1 1’. R2=x 2’. R2= R2-500 3’. x=R2 depositwithdraw

20. 20 Synchronization: How-To One approach: Disable interrupts Perform action Enable interrupts Advantages: Requires no hardware support Conceptually simple Disadvantages: Could cause starvation

21. 21 Synchronization: How-To, II Modern approach: atomic instructions Small set of instructions that cannot be interrupted Examples: Test-and-set (“TST”) if word contains given value, set to new value Compare-and-swap (“CAS”) if word equals value, swap old value with new Intel: LOCK prefix (XCHG, ADD, DEC, etc.) Used to implement locks

22. 22 Hardware Support OS ServiceHardware Support ProtectionKernel/User Mode Protected Instructions Base & Limit Registers InterruptsInterrupt Vectors System CallsTrap Instructions I/OInterrupt vectors, Memory- Mapping SynchronizationAtomic Instructions Virtual MemoryTranslation Lookaside Buffers SchedulingTimer

23. 23 Virtual Memory Provides illusion of complete access to RAM All addresses translated from physical addresses into virtual addresses OS loads pages from disk as needed Keeps track of which pages are in memory (“in core”) and which are on disk Many benefits, including: Allows users to run programs without loading entire program into RAM May not fit in entirety (think MS Office)

24. 24 Translation Lookaside Buffer First virtual memory systems performed address translation in software On every memory access! (s..l..o..w..) Modern CPUs contain hardware to do this: the TLB Hash-based scheme Maps virtual addresses to physical addresses Fast, fully-associative cache

25. 25 Hardware Support OS ServiceHardware Support ProtectionKernel/User Mode Protected Instructions Base & Limit Registers InterruptsInterrupt Vectors System CallsTrap Instructions I/OInterrupt vectors, Memory- Mapping SynchronizationAtomic Instructions Virtual MemoryTranslation Lookaside Buffers SchedulingTimer

26. 26 Scheduling & Timers OS needs timers for: Time of day CPU scheduling Fairness: limited quantum (e.g., 100ms) for each task When quantum expires, switch processes Uses interrupt vector

27. 27 Summary OS relies on hardware for many services Protection Interrupts Traps Synchronization Virtual memory Timers Otherwise impossible or impractically slow in software

28. 28 From Architecture to OS to User Architectural resources, OS services, user abstractions