1. 1 4 Bit Arithmetic Logic Unit Adithya V Kodati Hayagreev Pattabhiraman Vemuri Koneswara Advisor: Dave Parent 12/4/2005

2. 2 Abstract Designed a fully functional 4-bit ALU using Philips 74HC/HCT181 schematic. Frequency of operation: 250Mhz Power dissipated : 24.96 mW Area : 676x513uM 2 D-flip flops were used to connect the inputs and outputs

3. 3 Introduction The ALU is the basic building block of most digital circuits. Hence having a proper understanding and knowledge of how it should be designed and functions is necessary for a design engineer. Using CMOS design to implement the functions helps one to understand the design flow as well as adept use of Cadence software. This project also builds a strong foundation for other advanced design courses which use different processes to implement functionality.

4. 4 Project Details Performs full carry look-ahead for arithmetic operation. 16 arithmetic and 16 logical operations Works with active high as well as active low inputs All inputs and outputs are connected via D- flip flops.

5. 5 Table of functions Courtesy PHILIPS SEMICONDUCTOR

6. 6 Schematic and longest path

7. 7 Longest path transistor sizing CELLCint Cg or Cin of loadCg+Cint  phl CJNWNWP FF sF/cm^2cm AND4NOR25.00E-152.0000E-142.5000E-142.50E-104.23E-082.30E-044.72E-04 NAND25.00E-151.1786E-141.6786E-142.00E-104.23E-083.03E-042.70E-04 XOR 5.00E-159.6185E-151.4619E-144.00E-104.23E-083.58E-046.20E-04 INV5.00E-151.6424E-142.1424E-141.30E-104.23E-081.70E-043.06E-04 NOR4INV5.00E-158.0038E-151.3004E-141.00E-104.23E-082.18E-042.87E-04 NAND25.00E-158.4750E-151.3475E-142.35E-104.23E-081.71E-041.88E-04 NOR25.00E-156.0298E-151.1030E-142.00E-104.23E-089.13E-049.39E-04 AND5NOR25.00E-153.1075E-143.6075E-143.00E-104.23E-082.20E-044.40E-04 NAND35.00E-151.1073E-141.6073E-142.60E-104.23E-088.19E-044.82E-04 NOR2 5.00E-152.1823E-142.6823E-142.35E-104.23E-082.65E-045.71E-04 AND3INV5.00E-151.4023E-141.9023E-141.30E-104.23E-082.05E-042.75E-04 NAND35.00E-158.0554E-151.3055E-143.00E-104.23E-084.21E-042.46E-04 INV 5.00E-151.1189E-141.6189E-148.00E-114.23E-082.71E-044.91E-04

8. 8 SCHEMATIC

9. 9 LAYOUT

10. 10 LAYOUT VERSUS SCHEMATIC (LVS)

11. 11 LVS Report

12. 12 LVS report contd..

13. 13 Simulations

14. 14

15. 15 Important lessons learnt Divide the circuit into cells. Perform DRC and LVS at each stage. Confine usage of metal3 to the later stages of layout. Design floor plan and routing of major signals before you start the overall layout. Use Cadence lab to the maximum extent.

16. 16 Acknowledgements Professor Parent Thanks to Labtam’s Xlitepro for the remote login. Thanks to Cadence Design Systems for the VLSI lab.