1. Threshold Voltage Assignment to Supply Voltage Islands in Core- based System-on-a-Chip Designs Milestone 2: Steven Beigelmacher Gall Gotfried www.ece.cmu.edu/~ggall 03/23/2005

2. Overview Review What are we doing? How are we doing it? Parquet Code overview Closer look at the relevant portions What have we done? What worries us? Demo Milestones

3. Review Voltage islands are regions where nearby IP blocks use a supply voltage different from the full-chip supply We propose taking voltage islands in a core-based SoC design, and adding Vth assignments and latency measures A coarse-grained placement problem

4. Review Different classes of placement algorithms exist Integer Linear Programming, Recursive, Iterative We went with an iterative solver Want to avoid greedy algorithms Simulated annealing – locally bad choices can be globally good Parquet – S. Adya, H. Chan, I. Markov Pronunciation: pär-'kA to make of parquetry Parquetry -- work in the form of usually geometrically patterned wood laid or inlaid especially for floors http://vlsicad.eecs.umich.edu/BK/parquet

5. Review Simulated annealing loops are made up of two phases What are the set of perturbations I can make to the current solution? (move function) What is the relative “goodness” of that change? (cost function) Move Function Move block to spot (x,y), swap two blocks, block rotation, block scaling, etc

6. Review Cost Function Calculate a number quantifying the “goodness” of the solution How good a solution is will depend on the area, aspect ration, wire length, etc What are we doing? Modifying the move function to make moves creating voltage islands Modifying the cost function to take into account these voltage islands

7. Current State of Parquet Code contains no comments Only minimal support from the authors Primary author has moved on to industry Navigating the code has consumed most of our time Doxygen to the rescue: http://www.ece.cmu.edu/~ggall/parque t/index.html http://www.ece.cmu.edu/~ggall/parque t/index.html

8. Parquet Main Call Graph

9. Parquet Annealing Graph Annealer.cxx, for the curious

10. Selecting a Move Randomly picking which move to make Making the move

11. Checking the Cost Parquet uses different linear cost functions depending on emphasis of aspect ratio, wire length, or area AR and minWL AR minWL None Calculation of these delta components changes as t  0

12. Accepting a Move Accept good moves Else, accept bad moves with some probability that decreases as t  0 Once t equals 0, run a few more greedy iterations

13. Needed Parquet Modifications Node objects (blocks for placement) have been modified to include list of possible supply voltages, current supply voltage Input node file stores these voltages, which are read during the creation of the Parquet object

14. Parquet Obstacles Voltage islands depend on adjacency of blocks Need a way to determine of two blocks at the same Vdd can be bound without intersecting a block running at a different Vdd This might fall out easily from sequence- pairs. We’re looking into this

15. Next Set of Modifications Once we can detect voltage islands, need to account for them in the cost functions Will need to examine linear vs. quadratic, convergence issues, weights, etc Generate move functions that will push designs towards creating voltage islands Still feasible to do Vth and latency optimizations?

16. Demo Time! Output diagram now displays the voltage at which each block is currently running We can’t yet detect islands, so the annealer has no way to converge on solutions with islands at this time

17. Milestones Previous work exploration Begin implementing algorithm for Vdd island partitioning Deadline 02/23/2005 Extend Algorithm Create graphical interface to algorithm to ease understanding Extend algorithm to parse voltage assignments and generate output graphs Deadline 03/21/2005 Achieve Results Modify move and cost functions to account for supply voltage islands Test given benchmarks with voltage assignments and examine output graphs Extend modifications to include threshold voltages and examine output graphs Deadline 04/11/2005

18. You Got Questions We Got Answers