1. Vector Multiplication & Color Convolution Team Members Vinay Chinta Sreenivas Patil EECC - 731 VLSI Design Projects Dr. Ken Hsu

2. Goal A VLSI chip capable of 3*3 matrix multiplication or 3*3 digital convolution Design to operate at a frequency suitable for real-time video and image processing applications.

3. Applications Typically used in applications such as digital copiers where incoming color data needs to undergo unsharp masking for quality color output.  Data is converted into chrominance and luminance channels.  The RGB signals captured by the camera are linearly matrixed and processed for color sensitivity correction using 3*3 matrices.  After this, convolution operation is applied to luminance channel to enhance sharpness.

4. Multi-functionality Noise reduction, feature extraction, image enhancement, restoration and various other operations performed by linear filter (3*3 convolvers) Providing different kernels or matrices, it can be used for all these image processing operations. The VMCC is the single solution for all these functions.

5. Modes of Operation Mode 0: Color Matrixing Each output is weighted sum of three input words R, G, B which are the attributes of a single pixel. The output is valid each clock cycle if data is presented to the chip continuously

6. Color Matrixing

7. Modes of operation Mode 1: 3*3 2-D convolution Receives image data three pixels at a time in three consecutive pixel times, multiplies the 9 pixel values by the corresponding 9 coefficients stored in the static registers and computes the sum.

8. 2-D Convolution

9. Functional Block Diagram

10. Functional Blocks used in the project 10 - bit registers 10 x 10 - bit multipliers 20 - bit adders 10 - bit multiplexers Clock divider (÷3) Shift Register (3 stage 10 bits)

11. Results for the multiplier Multiplier is the largest combinational block in the design Combinational Area: 7145.1045 Non-combinational Area: 0 Total Cell Area: 7145.1298 Total Dynamic power : 7.6201 mW Number of cells: 419 Number of gates in critical path: 51

12. 9 Multiplier Design Latency = 6 Clock cycles

13. 9 Multiplier Design Precompiled structure Hardware used 10 - bit registers - 35 10 x 10 - bit multipliers- 9 20 - bit adders - 8 10 - bit multiplexers - 7

14. 9 Multiplier Design Post - Compiled structure (with low effort)

15. 9 Multiplier Design Post - Compiled structure (with high effort)

16. Modified Circuit - Block Diagram

17. 3 Multiplier Design Latency = 4 Clock cycles

18. 3 Multiplier Design Precompiled structure Hardware used 10 - bit registers - 6 10 x 10 - bit multipliers- 3 20 - bit adders - 2 10 – bit Shift registers - 3 ÷ 3 Clock Dividers- 1

19. 3 Multiplier Design Post - Compiled structure (with high effort)

20. Real-time operation - with a latency of six clock cycles (in original design) - with a latency of 4 clock cycles (in modified design) The operating speed suitable for real-time NTSC video processing. The MODE input selects either 3*3 matrix multiplication or 2-D convolution. Results Note: This speed has to be divided by factor of 3.

21. Features Two operations on a single chip. Matrix operations for color processing Convolution for filtering and enhancement. Real-time operation for NTSC signals.

22. Further Work Design of BIST for the design. Control Interface / Communicator Implementation of High Speed Multiplication and Additions algorithms. Optimize for Higher Speed

23. References 1. A Pipelined ASIC for Color Matrixing and Convolution, K. Hsu, LJ. D'Luna, H. Yeh, W.A. Cook, G.W. Brown 2. L. J. D'Luna, et al., A Digital Video Signal Post-Processor for Color Image Sensors, Proceedings of CICC 1989.24.2014. 3. Digital integrated circuits : a design perspective, Rabaey,Pearson Education, c2003 4. W. Wesley Peterson and E. J. Weldon, Jr., Error-Corecting Codes (2nd ed.) 1972, The MIT Press,Cambridge, Massachusetts, 1972, 5. VHDL : Programming By Example, Perry, Douglas L, McGraw-Hill, c2002 6. 3x3 Convolver with Run-Time Reconfigurable Vector Multiplier in Atmel AT6000 FPGAs. AT6000 FPGAs. Application Note (http://www.tecnun.com/asignaturas/tratamiento%20digital/convolver.pdf) 7. Digital Image Processing, Gonzalez, Rafael C., Woods, E. Richards. 2002 8. Introduction To VLSI Circuits And Systems, John P. Uyemura, 1952, J. Wiley, c2002 9. Fundamentals of digital logic with VHDL design, Brown, Stephen D, McGraw-Hill, c2000 10. Wikipedia, the free encyclopedia (http://en.wikipedia.org)

24. Questions ???