1. Dayle Kotturi SLC Integrationdayle@slac.stanford.edu April 29, 2004 Outline Motivation Key Components Status Update SLC / EPICS Timing Software Tasks Hardware Tasks Conclusions SLC Integration LCLS Facility Advisory Committee April 29-30, 2004

2. Dayle Kotturi SLC Integrationdayle@slac.stanford.edu April 29, 2004 Motivation for Integrating SLC / EPICS Many of the SLC high level applications running on the SLC control system are required for commissioning and operation. Sectors 20-30 of the existing SLC LINAC will be used with minimal modifications. The LINAC is instrumented and the data is in the SLC control system. No budget or schedule to replace the first two items. The SLC technology is dated and an upgrade path is highly desirable. EPICS provides a platform that is widely used that supports the requirements of a pulsed LINAC.

3. Dayle Kotturi SLC Integrationdayle@slac.stanford.edu April 29, 2004 Key Components of SLC / EPICS Integration Timing System Integration Support integration to the RF based timing Provide Beam Code and User Code information to EPICS environment Create an SLC-Aware IOC that can emulate the SLC Micro functions in an EPICS IOC, making all EPICS data available to existing SLC high level applications. Build on the EPICS Server that provides SLC data to an EPICS environment to provide existing SLC data in the LINAC for high level applications in the EPICS environment.

4. Dayle Kotturi SLC Integrationdayle@slac.stanford.edu April 29, 2004 Update: February 2004 – April 2004 Prior to February 2004 a timing integration meeting was held at SLAC to consider using the SLC timing front-end with an EPICS timing system. (PSI was considered) Design changed to include SLC-aware IOC Allowed new designs outside of CAMAC Caused extensive re-costing throughout the WBS Three design discussion meetings have been held to discuss SLC/EPICS integration An SLC expert, Tony Gromme, has provided significant detailed information to support the understanding of the effort

5. Dayle Kotturi SLC Integrationdayle@slac.stanford.edu April 29, 2004 Integrating SLC and EPICS Timing CPUCPU Beam Code + EPICS Time + EPICS Events LLRF (digitzer) 16 triggers CPUCPU EVREVR Diag 16 triggers IOC EVREVR CPUCPU EVREVR Power Supply Ctrl IOC CPUCPU Vacuum Ctrl Machine Protection Drive Laser Off SLC micro 476 MHz RF Reference Master Pattern Generator PNET (128 bit beam Code @ 360 Hz) FIDO 119 MHz w/ 360 Hz fiducial Nsec resolution on the timing gates produced from the Event Rcvr 50 psec jitter pulse to pulse Event generator passes along beam code data from SLC Event generator sends events to receivers including: 360 Hz, 120 Hz, 10 Hz and 1 Hz fiducials last beam pulse OK Machine mode EPICS time stamp Event receivers produce to the IOC interrupts on events data from the event generator in registers 16 triggers with configurable delay and width EVGEVG P N E T R C V R

6. Dayle Kotturi SLC Integrationdayle@slac.stanford.edu April 29, 2004 SLC Net “Micro” Communication CPUCPU LLRF (digitzer) CPUCPU EVREVR Diag IOC EVREVR CPUCPU EVREVR Pwr Supply Ctrl IOC SLC Alpha Apps Xterm CPUCPU Vacuum Ctrl SLC-Net over Ethernet Provides data to SLC Applications from EPICS Operates at 10 Hz (not beam synched) Requires significant development in the IOC to emulate SLC “micro” in the IOC On an application by application basis we will evaluate what functions to provide EVGEVG P N E T R C V R

7. Dayle Kotturi SLC Integrationdayle@slac.stanford.edu April 29, 2004 SLC to EPICS Communication CPUCPU LLRF (digitizer) CPUCPU EVREVR Diag IOC EVREVR CPUCPU EVREVR Power Supply Ctrl IOC Channel Access SLC Alpha Apps Xterm EPICS W/S Distributed Applications EPICS W/S Distributed Applications EPICS W/S Distributed Applications EPICS W/S Distributed Applications EPICS WS Distributed High Level Applications CPUCPU Vacuum Ctrl A channel access server in SLC provides data from existing SLC micros to EPICS applications All IOCs have both a channel access server to allow access and a client to have access Channel access provides read/write by all clients to all data with a server. All EPICS high level applications are channel access clients that may or may not have a server. EVGEVG P N E T R C V R

8. Dayle Kotturi SLC Integrationdayle@slac.stanford.edu April 29, 2004 Final Architecture – Incl. Feedback and MPS CPUCPU Beam Code + EPICS Time + EPICS Events LLRF 16 triggers CPUCPU EVREVR Diag 16 triggers IOC EVREVR HPRF I/O Boards CPUCPU EVREVR Pwr Supply Ctrl IOC Channel Access SLC Alpha Apps Xterm EPICS W/S Distributed Applications EPICS W/S Distributed Applications EPICS W/S Distributed Applications EPICS W/S Distributed Applications EPICS WS Distributed High Level Applications CPUCPU Vacuum Ctrl SLC-Net over Ethernet Fast Feedback over Ethernet? Machine Protection Drive Laser Off Beam Stop In EVGEVG P N E T R C V R

9. Dayle Kotturi SLC Integrationdayle@slac.stanford.edu April 29, 2004 SLC Aware Software Development Determine on an application-by-application basis if it is better to replicate the SLC micro communication capability or move the application into EPICS Straight through beam is needed 2 months per year Upfront effort and maintainability are the key factors Timing integration required early Decode 128 bit SLC beam code at 360 Hz into EPICS Provide a master pattern generator SLC communication tasks will be implemented one at a time, starting with the database exchange (dbex) Synchronous and buffered acquisition is required Is KIS-net required for straight through beam?

10. Dayle Kotturi SLC Integrationdayle@slac.stanford.edu April 29, 2004 SLC Aware Hardware Development Timing integration required early Decode 128 bit SLC beam code at 360 Hz into EPICS Maintain 20 psec jitter and provide 1 nsec gate resolution All new board designs depend on the ability to integrate timing hardware and SLC software Hardware designs that are dependent on this approach include: Low Level RF Beam Position Monitors & all other diagnostics Power Supply Controls Image Capture Motion Controls

11. Dayle Kotturi SLC Integrationdayle@slac.stanford.edu April 29, 2004 Conclusions Our key risk is in the design of an SLC-aware IOC and SLC to EPICS timing that will allow us to intermix the SLC and EPICS front-ends. This approach provides an incremental upgrade path for the SLC Linac. Expert support from ESD makes this design possible. Early prototypes are required to demonstrate this approach and provide platforms for the development of other subsystems such as LLRF, BPMs and Power Supply Control.