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Logic Synthesis Primer

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Presentation on theme: "Logic Synthesis Primer"— Presentation transcript:

1 Logic Synthesis Primer
Alan Mishchenko UC Berkeley

2 Outline Introduction to logic synthesis
Goals Exact vs. heuristic Sequential vs. combinational Technology-independent synthesis Optimization for area and delay Mapping Standard cells, LUTs, macro-cells Verification Conclusion

3 Goals of Synthesis Generating good circuit structure from
Truth tables, BDDs Irredundant sums-of-products (used in strash) Boolean decomposition (bidec) Converting decision trees into MUX circuits (muxes) Sums-of-products Factoring (used in strash) Kernel extraction (not implemented in ABC) fast_extract algorithm (command fx) Improving available circuit structure Technology-independent synthesis

4 Technology Independent Synthesis
AIG rewriting for area Scripts drwsat, compress2rs AIG rewriting for delay Scripts dc2, resyn2 High-effort delay optimization Perform SOP balancing (st; if –g –K 6) Follow up with area-recovery (resyn2) and technology mapping (map, amap, if) Iterate, if needed

5 Exact Synthesis Exact synthesis attempts to minimize the number of logic gates / logic levels needed to implement a given function Minimum solutions are known only for simple circuits, or circuits with special properties Minimum solutions are often not unique A new approach to synthesis is being developed, which uses pre-computed minimum solutions for practical functions up to 16 inputs to construct good (but not minimum) solutions for larger circuits See recent IWLS’14 paper for details

6 Sequential Synthesis Uses reachable state information to further improve the quality of results Reachable states are often approximated Types of AIG-based sequential synthesis Retiming (retime, dretime, etc) Detecting and merging sequentrial equivalences (lcorr, scorr, &scorr, etc) Negative experiences Sequential redundancy removal is often hard Using sequential don’t-cares in combinational synthesis typically gives very small improvement

7 Logic Synthesis for PLAs
Enter PLA (.type fd) into ABC using read Perform logic sharing extraction using fx If fx is complaining that individual covers are not prime and irredundant, try “bdd; sop; fx” After fx, convert shared logic into AIG and continue AIG-based synthesis and mapping Consider using high-effort synthesis with don’t-cares First map into 6-LUTs (if –K 6; ps), optimize (mfs2), synthesize with choices (st; dch) and map into 6-LUTs (if –K 6; ps) Iterate until no improvement, then remap into target technology To find description of PLA format, google for “Espresso PLA format”, for example:

8 Technology Mapping for SCs
Read library using read_genlib (for libraries in GENLIB format) read_liberty (for libraries in Liberty format) For standard-cells map: Boolean matching, delay-oriented, cells up to 5 inputs amap: structural mapping, area-oriented, cells up to 15 inputs If Liberty library is used, run topo followed by stime (accurate timing analysis) buffer (buffering) upsize; dnsize (gate sizing) Structural choices are an important way of improving mapping (both area and delay) Run “st; dch” before calling map or amap

9 Technology Mapping for LUTs
It is suggested to use mapper if –K <num> For area-oriented mapping, try “if -a” For delay-oriented mapping, try delay-oriented AIG-based synthesis with structural choices Structural choices are an important way of improving mapping (both area and delay) Run “st; dch” before calling if

10 Technology Mapping for Macrocells
Custom mapping options LUT structures composed of two or three LUTs if –S <XYZ> User-defined macro-cells up to 16 inputs, composed of LUTs, MUXes, and standard-cells Under development Minimizing circuit parameters number of factored-form literals (renode) number of cubes (renode –s) number of BDD nodes (renode –b) number of CNF clauses (write_cnf) As usual, structural choices can help

11 Verification Verification and synthesis are closely related and should be co-developed Combinational verification “r <file1>; cec <file2>” (small/medium circuits) “&r <file1.aig>; &cec <file2.aig> (large circuits) Sequential verification “r <file1>; dsec <file2>” Running cec or dsec any time during a synthesis flow compares the current version with the spec The spec is the circuit obtained from the original file

12 Future Work Improve usability of ABC
Develop mapping for user-specified macro-cells Develop more scalable technology-dependent synthesis

13 Conclusion Reviewed logic synthesis Proposed ABC commands for
Technology-independent synthesis Technology mapping Formal verification Discussed future developments

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