1. CS61C L27 Single-Cycle CPU Control (1) Garcia, Spring 2010 © UCB inst.eecs.berkeley.edu/~cs61c UC Berkeley CS61C : Machine Structures Lecture 27 Single-cycle CPU Control 2010-04-02 Success!  The large Hadron collider @ CERN is finally able to get subatomic particles colliding. No Higgs boson particle yet, but stay tuned. 16 years and 10 G$! Lecturer SOE Dan Garcia www.cs.berkeley.edu/~ddgarcia www.nytimes.com/2010/03/31/science/31collider.html

2. CS61C L27 Single-Cycle CPU Control (2) Garcia, Spring 2010 © UCB Review: A Single Cycle Datapath 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst Extender 3216 imm16 ALUSrcExtOp MemtoReg clk Data In 32 MemWr zero 01 0 1 = ALU 0 1 WrEnAdr Data Memory 5 Instruction Imm16RdRtRs nPC_sel instr fetch unit clk We have everything except control signals

3. CS61C L27 Single-Cycle CPU Control (3) Garcia, Spring 2010 © UCB Recap: Meaning of the Control Signals nPC_sel: “+4” 0  PC <– PC + 4 “br” 1  PC <– PC + 4 + {SignExt(Im16), 00 } Later in lecture: higher-level connection between mux and branch condition “n”=next imm16 clk PC 00 4 nPC_sel PC Ext Adder Mux Inst Address 0 1

4. CS61C L27 Single-Cycle CPU Control (4) Garcia, Spring 2010 © UCB Recap: Meaning of the Control Signals ExtOp:“zero”, “sign” ALUsrc:0  regB; 1  immed ALUctr:“ ADD ”, “ SUB ”, “ OR ” °MemWr:1  write memory °MemtoReg: 0  ALU; 1  Mem °RegDst:0  “rt”; 1  “rd” °RegWr:1  write register 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst Extender 3216 imm16 ALUSrc ExtOp MemtoReg clk Data In 32 MemWr 01 0 1 ALU 0 1 WrEnAdr Data Memory 5

5. CS61C L27 Single-Cycle CPU Control (5) Garcia, Spring 2010 © UCB RTL: The Add Instruction add rd, rs, rt MEM[PC]Fetch the instruction from memory R[rd] = R[rs] + R[rt]The actual operation PC = PC + 4Calculate the next instruction’s address oprsrtrdshamtfunct 061116212631 6 bits 5 bits

6. CS61C L27 Single-Cycle CPU Control (6) Garcia, Spring 2010 © UCB Instruction Fetch Unit at the Beginning of Add Fetch the instruction from Instruction memory: Instruction = MEM[PC] same for all instructions imm16 clk PC 00 4 nPC_sel PC Ext Adder Mux Inst Address Inst Memory Instruction

7. CS61C L27 Single-Cycle CPU Control (7) Garcia, Spring 2010 © UCB The Single Cycle Datapath during Add R[rd] = R[rs] + R[rt] oprsrtrdshamtfunct 061116212631 32 ALUctr= ADD clk busW RegWr=1 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst=1 Extender 3216 imm16 ALUSrc=0 ExtOp=x MemtoReg=0 clk Data In 32 MemWr=0 zero 01 0 1 = ALU 0 1 WrEnAdr Data Memory 5 Instruction Imm16RdRtRs nPC_sel=+4 instr fetch unit clk

8. CS61C L27 Single-Cycle CPU Control (8) Garcia, Spring 2010 © UCB Instruction Fetch Unit at the End of Add PC = PC + 4 This is the same for all instructions except: Branch and Jump imm16 clk PC 00 4 nPC_sel=+4 PC Ext Adder Mux Inst Address Inst Memory

9. CS61C L27 Single-Cycle CPU Control (9) Garcia, Spring 2010 © UCB Single Cycle Datapath during Or Immediate? oprsrtimmediate 016212631 R[rt] = R[rs] OR ZeroExt[Imm16] 32 ALUctr= clk busW RegWr= 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst= Extender 3216 imm16 ALUSrc= ExtOp= MemtoReg= clk Data In 32 MemWr= zero 01 0 1 = ALU 0 1 WrEnAdr Data Memory 5 Instruction Imm16RdRtRs nPC_sel= instr fetch unit clk

10. CS61C L27 Single-Cycle CPU Control (10) Garcia, Spring 2010 © UCB R[rt] = R[rs] OR ZeroExt[Imm16] oprsrtimmediate 016212631 Single Cycle Datapath during Or Immediate? 32 ALUctr= OR clk busW RegWr=1 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst=0 Extender 3216 imm16 ALUSrc=1 ExtOp=zero MemtoReg=0 clk Data In 32 MemWr=0 zero 01 0 1 = ALU 0 1 WrEnAdr Data Memory 5 Instruction Imm16RdRtRs nPC_sel=+4 instr fetch unit clk

11. CS61C L27 Single-Cycle CPU Control (11) Garcia, Spring 2010 © UCB The Single Cycle Datapath during Load? R[rt] = Data Memory {R[rs] + SignExt[imm16]} oprsrtimmediate 016212631 32 ALUctr= clk busW RegWr= 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst= Extender 3216 imm16 ALUSrc= ExtOp= MemtoReg= clk Data In 32 MemWr= zero 01 0 1 = ALU 0 1 WrEnAdr Data Memory 5 Instruction Imm16RdRtRs nPC_sel= instr fetch unit clk

12. CS61C L27 Single-Cycle CPU Control (12) Garcia, Spring 2010 © UCB The Single Cycle Datapath during Load R[rt] = Data Memory {R[rs] + SignExt[imm16]} oprsrtimmediate 016212631 32 ALUctr= ADD clk busW RegWr=1 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst=0 Extender 3216 imm16 ALUSrc=1 ExtOp=sign MemtoReg=1 clk Data In 32 MemWr=0 zero 01 0 1 = ALU 0 1 WrEnAdr Data Memory 5 Instruction Imm16RdRtRs nPC_sel=+4 instr fetch unit clk

13. CS61C L27 Single-Cycle CPU Control (13) Garcia, Spring 2010 © UCB The Single Cycle Datapath during Store? oprsrtimmediate 016212631 Data Memory {R[rs] + SignExt[imm16]} = R[rt] 32 ALUctr= clk busW RegWr= 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst= Extender 3216 imm16 ALUSrc= ExtOp= MemtoReg= clk Data In 32 MemWr= zero 01 0 1 = ALU 0 1 WrEnAdr Data Memory 5 Instruction Imm16RdRtRs nPC_sel= instr fetch unit clk

14. CS61C L27 Single-Cycle CPU Control (14) Garcia, Spring 2010 © UCB The Single Cycle Datapath during Store Data Memory {R[rs] + SignExt[imm16]} = R[rt] oprsrtimmediate 016212631 32 ALUctr= ADD clk busW RegWr=0 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst=x Extender 3216 imm16 ALUSrc=1 ExtOp=sign MemtoReg=x clk Data In 32 MemWr=1 zero 01 0 1 = ALU 0 1 WrEnAdr Data Memory 5 Instruction Imm16RdRtRs nPC_sel=+4 instr fetch unit clk

15. CS61C L27 Single-Cycle CPU Control (15) Garcia, Spring 2010 © UCB The Single Cycle Datapath during Branch? if (R[rs] - R[rt] == 0) then Zero = 1 ; else Zero = 0 oprsrtimmediate 016212631 32 ALUctr= clk busW RegWr= 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst= Extender 3216 imm16 ALUSrc= ExtOp= MemtoReg= clk Data In 32 MemWr= zero 01 0 1 = ALU 0 1 WrEnAdr Data Memory 5 Instruction Imm16RdRtRs nPC_sel= instr fetch unit clk

16. CS61C L27 Single-Cycle CPU Control (16) Garcia, Spring 2010 © UCB The Single Cycle Datapath during Branch if (R[rs] - R[rt] == 0) then Zero = 1 ; else Zero = 0 oprsrtimmediate 016212631 32 ALUctr= SUB clk busW RegWr=0 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst=x Extender 3216 imm16 ALUSrc=0 ExtOp=x MemtoReg=x clk Data In 32 MemWr=0 zero 01 0 1 = ALU 0 1 WrEnAdr Data Memory 5 Instruction Imm16RdRtRs nPC_sel=br instr fetch unit clk

17. CS61C L27 Single-Cycle CPU Control (17) Garcia, Spring 2010 © UCB Instruction Fetch Unit at the End of Branch if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ; else PC = PC + 4 oprsrtimmediate 016212631 What is encoding of nPC_sel? Direct MUX select? Branch inst. / not branch Let’s pick 2nd option Adr Inst Memory nPC_sel Instruction Zero nPC_sel Q: What logic gate? imm16 clk PC 00 4 PC Ext Adder Mux 0 1 MUX ctrl

18. CS61C L27 Single-Cycle CPU Control (18) Garcia, Spring 2010 © UCB Administrivia Administrivia?

19. CS61C L27 Single-Cycle CPU Control (19) Garcia, Spring 2010 © UCB Step 4: Given Datapath: RTL  Control ALUctr RegDst ALUSrc ExtOp MemtoRegMemWr Instruction Imm16RdRsRt nPC_sel Adr Inst Memory DATA PATH Control Op Fun RegWr

20. CS61C L27 Single-Cycle CPU Control (20) Garcia, Spring 2010 © UCB A Summary of the Control Signals (1/2) inst Register Transfer add R[rd]  R[rs] + R[rt];PC  PC + 4 ALUsrc = RegB, ALUctr = “ ADD ”, RegDst = rd, RegWr, nPC_sel = “+4” sub R[rd]  R[rs] – R[rt];PC  PC + 4 ALUsrc = RegB, ALUctr = “ SUB ”, RegDst = rd, RegWr, nPC_sel = “+4” ori R[rt]  R[rs] + zero_ext(Imm16); PC  PC + 4 ALUsrc = Im, Extop = “Z”,ALUctr = “ OR ”, RegDst = rt,RegWr, nPC_sel =“+4” lw R[rt]  MEM[ R[rs] + sign_ext(Imm16)];PC  PC + 4 ALUsrc = Im, Extop = “sn”, ALUctr = “ ADD ”, MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4” sw MEM[ R[rs] + sign_ext(Imm16)]  R[rs];PC  PC + 4 ALUsrc = Im, Extop = “sn”, ALUctr = “ ADD ”, MemWr, nPC_sel = “+4” beq if ( R[rs] == R[rt] ) then PC  PC + sign_ext(Imm16)] || 00 else PC  PC + 4 nPC_sel = “br”, ALUctr = “ SUB ”

21. CS61C L27 Single-Cycle CPU Control (21) Garcia, Spring 2010 © UCB A Summary of the Control Signals (2/2) addsuborilwswbeqjump RegDst ALUSrc MemtoReg RegWrite MemWrite nPCsel Jump ExtOp ALUctr 1 0 0 1 0 0 0 x Add 1 0 0 1 0 0 0 x Subtract 0 1 0 1 0 0 0 0 Or 0 1 1 1 0 0 0 1 Add x 1 x 0 1 0 0 1 x 0 x 0 0 1 0 x Subtract x x x 0 0 ? 1 x x optarget address oprsrtrdshamtfunct 061116212631 oprsrt immediate R-type I-type J-type add, sub ori, lw, sw, beq jump func op00 0000 00 110110 001110 101100 010000 0010 Appendix A 10 0000See10 0010We Don’t Care :-)

22. CS61C L27 Single-Cycle CPU Control (22) Garcia, Spring 2010 © UCB Boolean Expressions for Controller RegDst = add + sub ALUSrc = ori + lw + sw MemtoReg = lw RegWrite = add + sub + ori + lw MemWrite = sw nPCsel = beq Jump = jump ExtOp = lw + sw ALUctr[0] = sub + beq (assume ALUctr is 00 ADD, 01: SUB, 10: OR ) ALUctr[1] = or where, rtype = ~op 5  ~op 4  ~op 3  ~op 2  ~op 1  ~op 0, ori = ~op 5  ~op 4  op 3  op 2  ~op 1  op 0 lw = op 5  ~op 4  ~op 3  ~op 2  op 1  op 0 sw = op 5  ~op 4  op 3  ~op 2  op 1  op 0 beq = ~op 5  ~op 4  ~op 3  op 2  ~op 1  ~op 0 jump = ~op 5  ~op 4  ~op 3  ~op 2  op 1  ~op 0 add = rtype  func 5  ~func 4  ~func 3  ~func 2  ~func 1  ~func 0 sub = rtype  func 5  ~func 4  ~func 3  ~func 2  func 1  ~func 0 How do we implement this in gates?

23. CS61C L27 Single-Cycle CPU Control (23) Garcia, Spring 2010 © UCB Controller Implementation add sub ori lw sw beq jump RegDst ALUSrc MemtoReg RegWrite MemWrite nPCsel Jump ExtOp ALUctr[0] ALUctr[1] “AND” logic “OR” logic opcodefunc

24. CS61C L27 Single-Cycle CPU Control (24) Garcia, Spring 2010 © UCB Peer Instruction 1)MemToReg=‘x’ & ALUctr=‘sub’. SUB or BEQ? 2)ALUctr=‘add’. Which 1 signal is different for all 3 of: ADD, LW, & SW? RegDst or ExtOp? 12 a) SR b) SE c) BR d) BE

25. CS61C L27 Single-Cycle CPU Control (25) Garcia, Spring 2010 © UCB °5 steps to design a processor 1. Analyze instruction set  datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic Formulate Logic Equations Design Circuits Summary: Single-cycle Processor Control Datapath Memory Processor Input Output

26. CS61C L27 Single-Cycle CPU Control (26) Garcia, Spring 2010 © UCB Bonus slides These are extra slides that used to be included in lecture notes, but have been moved to this, the “bonus” area to serve as a supplement. The slides will appear in the order they would have in the normal presentation

27. CS61C L27 Single-Cycle CPU Control (27) Garcia, Spring 2010 © UCB 32 ALUctr = Clk busW RegWr = 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst = Extender Mux 32 16 imm16 ALUSrc = ExtOp = Mux MemtoReg = Clk Data In WrEn 32 Adr Data Memory 32 MemWr = ALU Instruction Fetch Unit Clk Zero Instruction 0 1 0 1 01 Imm16RdRsRt New PC = { PC[31..28], target address, 00 } nPC_sel= The Single Cycle Datapath during Jump optarget address 02631 J-typejump 25 Jump= TA26

28. CS61C L27 Single-Cycle CPU Control (28) Garcia, Spring 2010 © UCB The Single Cycle Datapath during Jump 32 ALUctr =x Clk busW RegWr = 0 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst = x Extender Mux 32 16 imm16 ALUSrc = x ExtOp = x Mux MemtoReg = x Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction 0 1 0 1 01 RdRsRt New PC = { PC[31..28], target address, 00 } nPC_sel=? Jump=1 Imm16 TA26 optarget address 02631 J-typejump 25

29. CS61C L27 Single-Cycle CPU Control (29) Garcia, Spring 2010 © UCB Instruction Fetch Unit at the End of Jump Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_sel imm16 Instruction 0 1 Zero nPC_MUX_sel New PC = { PC[31..28], target address, 00 } optarget address 02631 J-typejump 25 How do we modify this to account for jumps? Jump

30. CS61C L27 Single-Cycle CPU Control (30) Garcia, Spring 2010 © UCB Instruction Fetch Unit at the End of Jump Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_sel imm16 Instruction 0 1 Zero nPC_MUX_sel New PC = { PC[31..28], target address, 00 } optarget address 02631 J-typejump 25 Mux 1 0 Jump TA 4 (MSBs) 00 Query Can Zero still get asserted? Does nPC_sel need to be 0? If not, what? 26