1. EEM 486: Computer Architecture Lecture 3 Designing a Single Cycle Datapath

2. Lec 3.2 The Big Picture: Where are We Now?  The Five Classic Components of a Computer  Today’s Topic: Design a Single Cycle Processor Control Datapath Memory Processor Input Output

3. Lec 3.3 The Big Picture: The Performance Perspective  Performance of a machine is determined by: Instruction count Clock cycle time Clock cycles per instruction  Processor design (datapath and control) will determine: Clock cycle time Clock cycles per instruction CPI Inst. CountCycle Time

4. Lec 3.4 Single-cycle datapath  All instructions execute in a single cycle of the clock (positive edge to positive edge)  Advantage: a great way to learn CPU  Unrealistic hardware assumptions, slow clock period

5. Lec 3.5 Single cycle data paths: Assumptions Processor uses synchronous logic design (a “clock”) fT 1 MHz 1 μ s 10 MHz100 ns 100 MHz10 ns 1 GHz1 ns All state elements act like positive edge-triggered flip flops Clocks arrive at all flip flops simultaneously. DQ clk

6. Lec 3.6 Review: Edge-Triggered D Flip Flops DQ  Value of D is sampled on positive clock edge  Q outputs sampled value for rest of cycle. CLK D Q

7. Lec 3.7 How to Design a Processor: Step-by-Step 1. Analyze instruction set => datapath requirements Meaning of each instruction is given by the register transfers Datapath must include storage element for ISA registers -possibly more Datapath must support each register transfer 2. Select set of datapath components and establish clocking methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer 5. Assemble the control logic

8. Lec 3.8 The MIPS Instruction Formats  The three instruction formats : R-type I-type J-type  The different fields are: op: operation of the instruction rs, rt, rd: the source and destination register specifiers shamt: shift amount funct: selects the variant of the operation in the “op” field address / immediate: address offset or immediate value target address: target address of the jump instruction optarget address 02631 6 bits26 bits oprsrtrdshamtfunct 061116212631 6 bits 5 bits oprsrt immediate 016212631 6 bits16 bits5 bits

9. Lec 3.9 Step 1a: The MIPS-lite Subset for Today  ADD/SUB addU rd, rs, rt subU rd, rs, rt  OR Immediate: ori rt, rs, imm16  LOAD/STORE Word lw rt, rs, imm16 sw rt, rs, imm16  BRANCH beq rs, rt, imm16 oprsrtrdshamtfunct 061116212631 6 bits 5 bits oprsrtimmediate 016212631 6 bits16 bits5 bits oprsrtimmediate 016212631 6 bits16 bits5 bits oprsrtimmediate 016212631 6 bits16 bits5 bits

10. Lec 3.10 Step 1a: Executing MIPS Instructions - Fetch next inst from memory - Get ready for the next instruction opcodersrtrdfunctshamt - Decode fields to get a particular instruction - Retrieve register values (rs, rt) - Perform the operation (add, sub, or, lw, sw, beq) - Place the result in a register (rt/rd) / memory, or modify PC Instruction Fetch Instruction Decode Operand Fetch Execute Result Store

11. Lec 3.11 Step 1a: Logical Register Transfers  RTL gives the meaning of the instructions  All start by fetching the instruction op | rs | rt | rd | shamt | funct = MEM[ PC ] op | rs | rt | Imm16 = MEM[ PC ] inst Register Transfers ADDUR[rd] <– R[rs] + R[rt];PC <– PC + 4 SUBUR[rd] <– R[rs] – R[rt];PC <– PC + 4 ORiR[rt] <– R[rs] | zero_ext(Imm16); PC <– PC + 4 LOADR[rt] <– MEM[ R[rs] + sign_ext(Imm16)];PC <– PC + 4 STOREMEM[ R[rs] + sign_ext(Imm16) ] <– R[rt];PC <– PC + 4 BEQif ( R[rs] == R[rt] ) then PC <– PC + 4 + [sign_ext(Imm16) || 00] else PC <– PC + 4

12. Lec 3.12 Step 1: Requirements of the Instruction Set  Memory instruction & data  Registers (32 x 32) read RS read RT Write RT or RD  PC  Extender  Add and Sub registers or register and extended immediate  Logical Or of a register and extended immediate  Add 4 or extended immediate to PC

13. Lec 3.13 Step 2: Components of the Datapath  Combinational Elements  Storage Elements Clocking methodology

14. Lec 3.14 Combinational Logic Elements (Basic Building Blocks)  Adder  MUX  ALU 32 A B Sum Carry 32 A B Result OP 32 A B Y Select Adder MUX ALU CarryIn

15. Lec 3.15 Storage Element: Register (Basic Building Block)  Register Similar to the D Flip Flop except -N-bit input and output -Write Enable input Write Enable: -Negated (0): Data Out will not change -Asserted (1): Data Out becomes Data In Clk Data In Write Enable NN Data Out

16. Lec 3.16 Storage Element: Register File  Register File consists of 32 registers: Two 32-bit output busses: busA and busB One 32-bit input bus: busW  Register is selected by: RA (number) selects the register to put on busA (data) RB (number) selects the register to put on busB (data) RW (number) selects the register to be written via busW (data) when Write Enable is 1  Clock input (CLK) The CLK input is a factor ONLY during write operation During read operation, behaves as a combinational logic block: -RA or RB valid => busA or busB valid after “access time.” Clk busW Write Enable 32 busA 32 busB 555 RWRARB 32 32-bit Registers

17. Lec 3.17 Storage Element: Idealized Memory  Memory (idealized) One input bus: Data In One output bus: Data Out  Memory word is selected by: Address selects the word to put on Data Out Write Enable = 1: address selects the memory word to be written via the Data In bus  Clock input (CLK) The CLK input is a factor ONLY during write operation During read operation, behaves as a combinational logic block: -Address valid => Data Out valid after “access time.” Clk Data In Write Enable 32 DataOut Address

18. Lec 3.18 Clocking Methodology  All storage elements are clocked by the same clock edge  Being physical devices, flip-flops (FF) and combinational logic have some delays Gates: delay from input change to output change Signals at FF D input must be stable before active clock edge to allow signal to travel within the FF, and we have the usual clock-to-Q delay  “Critical path” (longest path through logic) determines length of clock period........................ Clk Don’t Care SetupHoldSetupHold

19. Lec 3.19 Step 3: Assemble Datapath Meeting Requirements  Register Transfer Requirements  Datapath Assembly  Instruction Fetch  Read Operands and Execute Operation

20. Lec 3.20 3a: Overview of the Instruction Fetch Unit  The common RTL operations Fetch the Instruction: mem[PC] -PC == Program Counter, points to next instruction Update the program counter: -Sequential Code: PC <- PC + 4 -Branch and Jump: PC <- “something else” 32 Instruction Word Address Instruction Memory PC Clk Next Address Logic

21. Lec 3.21 Straight-line Instruction Fetch 32 Addr Data 32 Instr Mem Why +4 and not +1? CLK Address Data IMem[PC + 8] IMem[PC + 4] IMem[PC] PC + 8 PC + 4 PC op target address 02631 6 bits26 bits oprsrtrdshamtfunct 061116212631 6 bits 5 bits oprsrt immediate 016212631 6 bits16 bits5 bits

22. Lec 3.22 3b: Add & Subtract  R[rd] <- R[rs] op R[rt] Example: addU rd, rs, rt Ra, Rb, and Rw come from instruction’s rs, rt, and rd fields ALUctr and RegWr: control logic produces after decoding the instruction 32 Result ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers RsRtRd ALU oprsrtrdshamtfunct 061116212631 6 bits 5 bits

23. Lec 3.23 How data flows after posedge 32 RegFile 32 WE 32 5 Ra 5 Rb 5 Rw 32 ALUALU op Control Logic AddrData Instr Mem D PC Q Adder 4

24. Lec 3.24 Register-Register Timing: One complete cycle 32 Result ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers RsRtRd ALU Clk PC Rs, Rt, Rd, Op, Func Clk-to-Q ALUctr Instruction Memory Access Time Old ValueNew Value RegWrOld ValueNew Value Delay through Control Logic busA, B Register File Access Time Old ValueNew Value busW ALU Delay Old ValueNew Value Old ValueNew Value Old Value Register Write Occurs Here

25. Lec 3.25 3c: Logical Operations with Immediate  R[rt] <- R[rs] op ZeroExt[imm16] oprsrtimmediate 016212631 6 bits16 bits5 bits 32 Result ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs ZeroExt Mux RtRd RegDst Mux 32 16 imm16 ALUSrc ALU Rt?

26. Lec 3.26 3d: Load Operations  R[rt] <- Mem[R[rs] + SignExt[imm16]] E.g.: lw rt, rs, imm16 oprsrtimmediate 016212631 6 bits16 bits5 bits 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs RtRd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Clk Data In WrEn 32 Adr Data Memory 32 ALU MemWr Mu x W_Src ?? Rt?

27. Lec 3.27 3e: Store Operations  Mem[ R[rs] + SignExt[imm16] ] <- R[rt] E.g.: sw rt, rs, imm16 oprsrtimmediate 016212631 6 bits16 bits5 bits 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Clk Data In WrEn 32 Adr Data Memory MemWr ALU 32 Mu x W_Src

28. Lec 3.28 3f: The Branch Instruction  beqrs, rt, imm16 mem[PC]Fetch the instruction from memory Equal <- R[rs] == R[rt]Calculate the branch condition if (Equal)Calculate the next instruction’s address -PC <- PC + 4 + ( SignExt(imm16) x 4 ) else -PC <- PC + 4 oprsrtimmediate 016212631 6 bits16 bits5 bits

29. Lec 3.29 Datapath for Branch Operations  beq rs, rt, imm16Datapath generates condition (equal) oprsrtimmediate 016212631 6 bits16 bits5 bits 32 imm16 PC Clk 00 Adder Mux Adder 4 nPC_sel Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Equal? Cond PC Ext Inst Address

30. Lec 3.30 Putting it All Together: A Single Cycle Datapath imm16

31. Lec 3.31 A Single Cycle Datapath

32. Lec 3.32 An Abstract View of the Critical Path  Register file and ideal memory: The CLK input is a factor ONLY during write operation During read operation, behave as combinational logic: -Address valid => Output valid after “access time.” Critical Path (Load Operation) = PC’s Clk-to-Q + Instruction Memory’s Access Time + Register File’s Access Time + ALU to Perform a 32-bit Add + Data Memory Access Time + Setup Time for Register File Write + Clock Skew Clk 5 RwRaRb 32 32-bit Registers Rd ALU Clk Data In Data Address Ideal Data Memory Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 16 Imm 32 A B Next Address

33. Lec 3.33 An Abstract View of the Implementation Data Out Clk 5 RwRaRb 32 32-bit Registers Rd ALU Clk Data In Data Address Ideal Data Memory Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 32 A B Next Address Control Datapath Control Signals Conditions

34. Lec 3.34 Steps 4 & 5: Implement the control Next time

35. Lec 3.35 Summary  5 steps to design a processor 1. Analyze instruction set => datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic  MIPS makes it easier Instructions same size Source registers always in same place Immediates same size, location Operations always on registers/immediates  Single cycle datapath => CPI=1, CCT => long  Next time: implementing control