3 Reversible Permutative logic Gates and Circuits 4/17/2017Reversible Permutative logic Gates and CircuitsA logic gate is reversible ifEach input is mapped to a unique outputIt permutes the set of input valuesA combinational logic circuit is reversible if it satisfies the following:Has only one Fanout,Uses only reversible gates,No feedback path,has as many input wires as output wires, and permutes the input values.
4 Basic Reversible Gates 4/17/2017Basic Reversible GatesNOT gateControlled-NOT or Feynman gatea b a c
5 Basic Reversible Gates 4/17/2017Basic Reversible GatesToffoli gate (Controlled-Controlled NOT gate)a b c a b f
6 Basic Reversible Gates 4/17/2017Basic Reversible GatesSwap gateImplementation of Swap gate using controlled-NOTWrite equations of intermediate state
7 Basic Reversible Gates 4/17/2017Basic Reversible GatesFredkin gate (Controlled SWAP gate)a b c a f g
8 Algorithms for Synthesis of Reversible Logic Circuits 4/17/2017Algorithms for Synthesis of Reversible Logic CircuitsI have given adequate background on reversible logic gates, lets explore the algorithms for synthesis of reversible logic circuits
9 Popular Algorithms for Synthesis of Reversible Logic Circuits 4/17/2017Popular Algorithms for Synthesis of Reversible Logic CircuitsMMD: Transformation basedGupta-Agrawal-Jha: PPRM basedMishchenko-Perkowski: Reversible wave cascadeKerntopf: Heuristics basedWille: BDD based synthesisI will describe in detail PPRM based algorithm in next few foils and then we will discuss limitations of these algorithm and how our lattice based synthesis algorithm is better compared to these algorithms.
10 reed-mulLER EXPANSION IN SYNTHESIS OF REVERSIBLE CIRCUITS
11 IDEA: use reed-mulLER EXPANSION IN SYNTHESIS OF REVERSIBLE CIRCUITS A New Representation is Reed-Muller Expansion (Positive Polarity Reed-Muller). This idea appeared for the first time in paper of Aggrawal and Jha, this paper was a competitor to MMD algorithm. Now we design a new algorithm which takes into account multi-level expansion for reversible circuits.
12 Example of Agrawal-Jha Algorithm 4/17/2017Example of Agrawal-Jha Algorithmc b aco bo aoPPRM form for each output in terms ofInput variables are given as follows andnode is createdReversible function specification is given as a truth table shown hereOutput c0, b0 and a0 are derived using EXORCISM-2 developed at PSU and parent node is created
13 Agrawal-Jha Algorithm (cont..) 4/17/2017Parent node is explored by examining each output variable in the PPRM expansion.Factors are searched in the PPRM expansions that do not contain the same input variable.For example in the expansion below appropriate terms are “c” and “ac”The substitution is performed asIn this example OR
15 Agrawal-Jha Algorithm (cont..) 4/17/2017Agrawal-Jha Algorithm (cont..)New nodes are created based on substitution
16 Next stage of Aggrawal-Jha algorithm 4/17/2017Next stage of Aggrawal-Jha algorithm
17 Next stage of Aggrawal-Jha algorithm 4/17/2017Next stage of Aggrawal-Jha algorithm
18 Solution found by the Aggrawal-Jha algorithm 4/17/2017Solution found by the Aggrawal-Jha algorithm
19 Problem with Current Synthesis Approaches 4/17/2017Problem with Current Synthesis ApproachesCommon problem with current approaches: they invariably use nxn Toffoli gates, that might imposes technological limitations.High Quantum cost of Toffoli gates with many inputs.Synthesize only reversible functions, not Boolean functions that is not reversible.
20 Quantum Cost of 4x4 Toffoli Gate 4/17/2017Quantum Cost of 4x4 Toffoli GateImplementation of 4x4 Toffoli gate with Quantum realizable 2x2 primitives such as controlled-V, controlled-NOT, controlled-V+.
22 Expansions Rules for Lattice DIAGRAAMS 4/17/2017Expansions Rules for Lattice DIAGRAAMSPositive Davio Tree can be created by expanding PPRM function using positive Davio expansion.Positive Davio Lattice is created by performing joining operation for neighboring cells at every level.Other Lattices can be created using similar method but using expansions such as Shannon or Negative Davio expansions or combination of them.
23 Creating Quantum Array from Lattices 4/17/2017On the previous foils I showed representation of the Davio and Shannon cells as cascade of reversible gates.Next I present unique method to create Quantum Array from Positive Davio Lattice.The same approach can be used for other Lattices.
27 Quantum Array Representation 4/17/2017Quantum Array Representationabcddgarbagea1Ågarbage1ad1Ågarbage1bab1Ågarbage1We are adding gasbags but it is little cost since our function was not a reversible function to start with and we use only 3x3 Toffoli gateAdd foil for Toffoli gate built from controlled-V and controlled-V hermitianTalk about optimizationaabdbÅbddabÅgarbageabcdcdacbcabdaddb1Å1functionadabddb1Å
30 Advantages of Lattice to QA 4/17/2017Advantages of Lattice to QAReversible circuit synthesized with only 3x3 Toffoli gates.Generates reversible circuit for any ESOP.Adds ancilla bits but overall cost of the circuit will be lower due to use of low cost 3x3 Toffoli gates.
31 Calculating Single-Output Shannon Lattice for Completely Specified Boolean Function.
32 Calculating Multi-Output Shannon Lattice for Completely Specified Boolean Function.
33 Calculating Multi-Output Shannon Lattice for Completely Specified Boolean Function.
34 DIPAL GATES, DIPAL GATE FAMILIES AND THEIR ARRAYS
35 Representation of pdv cell as a toffoli gate 4/17/2017Representation of pdv cell as a toffoli gate
36 Development of Dipal gate 4/17/2017abcfÅ=Shannon cellDipal cellrepresentation withreversible gatesDipal gate is a reversibleequivalent of Shannon cellThere are 23! = 8! = x3 Reversible logic functions, however only handful ofthem shown earlier are useful for synthesis purpose.Find the reversible counterpart of well-known structures BDD, Lattices, KFDDShow Dipal cell is between Toffoli and Fredkin
37 Development of Dipal gate (cont..) 4/17/2017Development of Dipal gate (cont..)abcfÅ=Shannon cell with negativevariableDipal cell with negativevariable represented withreversible gates
38 Development of Dipal gate 4/17/2017abcfÅ=Shannon cellDipal cellrepresentation withreversible gatesDipal gate is a reversibleequivalent of Shannon cellThere are 23! = 8! = x3 Reversible logic functions, however only handful ofthem shown earlier are useful for synthesis purpose.
43 Results with Pdv Lattice and comparison with MMD and AJ results Benchmark#Real inputs#Garbage inputs#Gates LatticeCost LatticeCPU time Lattice#Gates DMMCost DMM#Gates AJCost AJ2to554311070.121520100rd32318< 0.01rd5311391675131163_171021612146sym341500.3762NA5mod55890914mod518ham379xor5Xnor5decod24230Cycle10_218086027.9191198ham7220.1023812468
44 Results with Pdv Lattice and comparison with MMD and AJ results (cont Benchmark#Real inputs#Garbage inputs#Gates LatticeCost LatticeCPU time Lattice#Gates DMMCost DMM#Gates AJCost AJgraycode665< 0.01graycode10109graycode202019nth_prime3_inc34nth_prime4_inc16481258nth_prime5_inc29910.222678alu217181144_49520.041361hwb428631535hwb524961.2104hwb6321282.042140pprm133
49 Fig. 2. Circuit for function FX2 created with our method for traditional cost function calculation that does not take Ion Trap technology constraints into account.
50 Nearest Linear Node Model All gates are realized only on neighbors, but we have to add many SWAP gatesFig. 3. Circuit from Figure 2 modified with adding SWAP gates for new cost function calculation that does take Ion Trap technology constraints into account, with XX gates added. It has 36 SWAP gates added to realize LNNM.
51 Example of Positive Davio Lattice from [Perkowski97d] Example of Positive Davio Lattice from [Perkowski97d]. Positive Davio Expansion is applied in each node. Variable d is repeated
52 Transformation of function F3(a,b,c) from classical Positive Davio Lattice to a Quantum Array with Toffoli and SWAP gates. Each SWAP gate is next replaced with 3 Feynman gates.(a) intermediate form, (b) final Quantum Array.
53 Intermediate Structure with Dipal Gate 4/17/2017Intermediate Structure with Dipal Gate
54 Another Representation of Quantum Array with Dipal Gate 4/17/2017Another Representation of Quantum Array with Dipal Gate
55 Layered Diagram using Dipal Gate 4/17/2017Layered Diagram using Dipal GateGeneral layout of the layered diagramEach box represents a gate from family of Dipal gate
56 General Pattern of Circuit with Dipal Gate 4/17/2017General Pattern of Circuit with Dipal Gate
57 Quantum cost based On 1d model Benchmark#Gates LatticeCost Lattice#Gates with SWAP insertion for LatticeCost with SWAP gates for Lattice#Gates DMMCost DMM#Gates with SWAP insertion for MMDCost with SWAP gates for MMD2to5311076119715155rd324820614rd531139441381675722733_1710213312186sym341505621662782365mod558176790482044mod530513Ham337Xor5Xnor5decod2442Cycle10_218086030612381911981991738Ham722112238179249
58 Quantum cost based On 1d model Benchmark#Gates LatticeCost Lattice#Gates with SWAP insertion for LatticeCost with SWAP gates for Lattice#Gates DMMCost DMM#Gates with SWAP insertion for MMDCost with SWAP gates for MMDGraycode65Graycode109Graycode2019Nth_prime3_inc4612Nth_prime4_inc16482060581876Nth_prime5_inc2991391212678128384Alu177234_49524112740130hwb4281563129hwb524964415610464224hwb6327224842140144446pprm133
59 GENERALIZED REGULARITIES FOR QUANTUM AND NANO-TECHNOLOGIES
60 Ion-Trap Layout Interaction between two ions Single ion 4/17/2017Ion-Trap LayoutInteraction between two ions(a)(b)(c)Single ionVarious regular structures are technically possible, single dimensional vector is the one that is most often discussed(d)
73 The transformations of blocks of quantum gates to the pulses level.
74 Transformation of the circuit realized in Fig. 7 using Toffoli gate Transformation of the circuit realized in Fig. 7 using Toffoli gate. Each Toffoli and SWAP gates are replaced by quantum CNOT and CV/CV+ quantum gates and rearranged to satisfy the neighborhood requirements of Ion trap.
76 New type of FPGA in CMOSIn classical CMOS logic one can design a regular array, such as a form of FPGA, which realizes Shannon, positive Davio and negative Davio inside one cell. Such array is highly testable We can try to design something similar in quantum and reversible logic circuits.
77 Design of SRFPGA cell4/17/2017Dipal completed his MS in December 2000 with thesis on “Method for Self-Repair of FPGAs”.I adapted concept of Lattices which were developed Dr. Perkowski and Dr. Jeske to design FPGA like regular structure in VLSIThis cell can be mapped to Shannon, positive Davio, negative Davio and other logic gates.
78 General idea of SRFPGA architecture 4/17/2017General idea of the SRFPGA architecture, each circle represents cell shown on the previous foil.Row and column decoders are for memory addressingThe next foil shows actual physical design of the SRFPGA
80 Faults observed during column test 4/17/20171Faults observed during column testC = 2.Test outputVar1var2var3var4var5var6var7var8var9var10var11var12var13var14var15var16Inputesvcor1Faults observedduringdiagonal testD = 2111Testoup11111111Total number ofFaults N = C * D= 2 * 2 = 4.11111111111111111Input test vector
81 This approach can be extended to reversible and quantum logic cicuits. 4/17/2017Dipal developed a unique test that identifies any number of faulty cell in the FPGARepair is based on redundancy-repair where identified faulty cells are replaced with unused good cell in the structureLater Dipal adapted concept of lattice and synthesis methodology for designing reversible logic circuits.His method of reversible circuit design resolves many issues that are not yet addressed by any other researchersThis approach can be extended to reversible and quantum logic cicuits.
83 ConclusionsExperimental results proved that our algorithm produced better results in terms of quantum cost compared to other contemporary algorithms for synthesis of reversible logic.New gate family called Dipal gatePresented new synthesis method with layered diagrams.More accurate technology specific cost model for 1D qubit neighborhood architecture.
84 4/17/2017CONCLUSIONSA new method based of lattice diagram to synthesize reversible logic circuit with 3x3 Toffoli gates.A new family of gates called Dipal Gates.New diagrams called layered diagram that uses family of Dipal gate for synthesis of reversible logic function.Software for creating Lattice diagrams and software for creating quantum array from Lattice (Lattice to QA).Program to implement a variant of MMD algorithm.
85 Possible Projects Generalize to ternary logic 4/17/2017Possible ProjectsGeneralize to ternary logicGeneralize to all Dipal Gate Family gates.Realization with low level pulses for NMR technology.Development of a concept of reversible/quantum FPGA similar to SRFPGAExtend Agrawal-Jha method for factorized circuits.Extend the methods to many-output circuits.
86 What to remember? Use of PPRM in synthesis of reversible circuits. The main idea of Agrawal-Jha algorithm.How AJ algorithm can be improved?How this algorithm can be extended to Fredkin gates?Expansions Rules for Lattice DiagramsCreating Positive Davio LatticeCreating Negative Davio LatticeCreating Lattice for arbitrary function with a mixture of Davio and Shannon Expansions.Lattices for symmetric functions.Transforming Positive Davio Lattice to a quantum array (circuit) for single output functions.
87 What to remember?Transforming Positive Davio Lattice to a quantum array (circuit) for single output functions.Transforming Positive Davio Lattice to a quantum array (circuit) for multi-output functions.Dipal gate and Dipal gate family.Regular structures and their use in quantum computing.Regularity versus LNNM model.Multiple-valued Lattices for ternary logic.FPGA based on 3*3 lattices and can they be adapted to quantum and reversible circuits.Decomposition to pulses. Relation to quantum costs.