1. Test Wrapper Designs for the Detection of Signal Integrity Faults on Core External Interconnects of SOCs Qiang Xu and Yubin ZhangKrishnendu Chakrabarty The Chinese University of Hong Kong Duke University

2. Outline Introduction Prior work and motivation Overshoot detector Wrapper design for interconnect SI test Experimental results Conclusion

3. Signal Integrity

4. Impact of Technology Scaling Crosstalk Serious crosstalk Interconnect Shrinking feature size

5. Signal Integrity Problem Signal integrity is a major concern!

6. Testing SOC Interconnects

7. Typical WOC for Interconnect SI Test Simultaneous aggressor transitions in test mode Different from functional mode

8. Impact of Aggressor Alignment on Crosstalk Transition timing of aggressors/victim significantly affects signal integrity Need for skewed transitions to avoid under-testing

9. Prior Overshoot Detector Cross-coupled differential amplifier Test_Mode signal as control of source current Hysteresis property Input-dependent detection Cannot detect overshoot in all cases! Source: M. Nourani and A. Attarha, TCAD’02

10. Motivation Prior SI test techniques –simultaneous transitions in test mode may result in under-testing. –cannot detect overshoot in all cases. We need –wrapper input cell that can detect overshoot and delay faults in all cases. –wrapper output cell that can apply skewed transitions.

11. Proposed Overshoot Detector Maintain hysteresis property Self-biased amplifier, higher resolution Reset mechanism Can detect overshoot in all cases

12. Comparison of Overshoot Detectors

15. Wrapper Input Cell Equipped with overshoot detector One extra FF as delay detector (FF1).

16. Wrapper Input Cell Equipped with overshoot detector One extra FF as delay detector (FF1). Save test data

17. Wrapper Input Cell Equipped with overshoot detector One extra FF as delay detector (FF1). Save test data Shift out result

18. Test Strategy I

20. Functional path

21. Test Strategy II

22. Test path

23. Controlled-Delay Element for Skewed-Transition

24. Proposed Wrapper Output Cell

26. Experimental Setup 90 nm technology with 1V power supply 5 mm long victim with 5 aggressors, each coupling for a 1 mm length On the eighth metal layer with typical parameter

27. Experimental Results with Previous WOC 0.556 ns

28. Experimental Results with Proposed WOC 0.595 ns 0.614 ns with 2 delay paths with 4 delay paths

29. Experimental Results with Proposed WOC – Cont. 0.627 ns 0.622 ns with 6 delay paths with 8 delay paths

30. Discussion Benefits –Enhanced signal-integrity fault detection capability Costs –DfT area overhead –test time –Possible over-testing

31. Conclusion Signal integrity is a major concern for today’s SoC interconnects We have proposed novel test wrappers that –Detect all kinds of overshoots –Apply skewed-transitions for aggressors/victim groups –Have moderate overhead

32. Q & A