1. 1 of 14 1/15 Design Optimization of Multi-Cluster Embedded Systems for Real-Time Applications Paul Pop, Petru Eles, Zebo Peng, Viaceslav Izosimov Embedded Systems Lab (ESLAB) Linköping University, Sweden Magnus Hellring, Olof Bridal Dept. of Electronics and Software Volvo Technology Corp., Göteborg, Sweden

2. 2 of 14 2/15... Factory Systems Heterogeneous Networks Distributed Heterogeneous System... Heterogeneous Networks Multi-Cluster Systems... NoCs Automotive Electronics...

3. 3 of 14 3/15 Distributed Safety-Critical Applications... Gateway  Applications distributed over heterogeneous networks are difficult to...  Analyze (guaranteeing timing constraints)  Design (partitioning, mapping, bus access optimization)  Applications distributed over the heterogeneous networks  Reduce costs: use resources efficiently  Requirements: close to sensors/actuators [DATE’03] This paper!

4. 4 of 14 4/15 Outline  Motivation  System architecture and application model  Scheduling for multi-clusters [DATE’03]  Design optimization problems  Partitioning  Mapping  Bus access optimization  Optimization strategy  Experimental results  Contributions and Message

5. 5 of 14 5/15 S0S0 S1S1 S2S2 SGSG S0S0 S1S1 S2S2 SGSG TDMA Round Cycle of two rounds Slot Time Triggered Protocol (TTP)  Bus access scheme: time-division multiple-access (TDMA)  Schedule table located in each TTP controller: message descriptor list (MEDL) Controller Area Network (CAN)  Priority bus, collision avoidance  Highest priority message wins the contention  Priorities encoded in the frame identifier Hardware Architecture Gateway... Time-triggered cluster  Static cyclic scheduling  Time-triggered protocol Event-triggered cluster  Fixed priority preemptive scheduling  Controller area network protocol

6. 6 of 14 6/15 CPU NGNG Out CAN TTP Controller S1S1 SGSG Round2 P4P4 P1P1 CPU N1N1 TTP Controller MBI CPU MBI CAN Controller CPU N2N2 CAN Controller T m1m1 m2m2 m1m1 S1S1 SGSG Out TTP T P2P2 P3P3 Out N2 m3m3 m3m3 Software Architecture... Time-triggered cluster Event-triggered cluster Gateway

7. 7 of 14 7/15 Multi-Cluster Scheduling [DATE’03] Application, Partitioning, Mapping, Architecture TT Bus Configuration Priorities Schedule Tables Response times Static Scheduling Multi-Cluster Scheduling Offsets Response Times Response Time Analysis  MultiClusterScheduling algorithm  Schedulability analysis: communication delays through the gateway  Scheduling: cannot be addressed separately for each cluster

8. 8 of 14 8/15 Problem Formulation  Input  System architecture  Application  Partial partitioning and mapping, based on the designer’s experience Application: set of process graphs... Architecture: Multi-cluster  Output  Design implementation such that the application is schedulable  Partitioning for each un-partitioned process  Mapping for each un-mapped process  Priorities for ET messages  TDMA slot sequence and sizes for the TT bus  Priorities for ET processes  Schedule table for TT messages Partitioning and mapping Communication infrastructure Scheduling information

9. 9 of 14 9/15 P4P4 P5P5 P3P3 P6P6 P2P2 P1P1 N1N1 Missed (faster) N 2 (slower) N 3 Met Motivational Example #1 N2N2 N3N3 TTCETC N1N1 CAN TTP P3P3 P6P6 P5P5 P4P4 P2P2 P1P1 P1P1 P2P2 P3P3 P4P4 N1N1 N2N2 XX X 50 70 40 90 X P5P5 X40 N3N3 P6P6 70 X X X X X40X P4P4 P5P5 P3P3 P6P6 P2P2 P1P1 N1N1 P4P4 Preempted (faster) N 2 (slower) N 3 Met Preemption not allowed P3P3 P4P4 P4P4 P6P6 P5P5 P2P2 P1P1 N1N1 Preempted (faster) N 2 (slower) N 3 Met Deadline for P 6 Deadline for P 5 In which cluster to place process P 4 ?

10. 10 of 14 10/15 P1P1 N1N1 P3P3 TTP S2S2 N2N2 S3S3 SGSG SGSG S3S3 S1S1 SGSG P2P2 Missed S2S2 S3S3 S1S1 m1m1 m2m2 N3N3 CAN NGNG N4N4 Motivational Example #2 P1P1 P3P3 P2P2 m1m1 m2m2 P1P1 P2P2 P3P3 N1N1 N2N2 20X X X 40 X N4N4 X 50 X N3N3 X X 20 N3N3 N4N4 TTCETC N2N2 CAN TTP N1N1 NGNG Where to map process P 2 ? Met P1P1 N1N1 P3P3 TTP S2S2 T CAN N4N4 P2P2 NGNG S2S2 SGSG S2S2 S3S3 S1S1 SGSG T S2S2 S3S3 S1S1 N4N4 N3N3 m1m1 m1m1 m2m2 m2m2 N2N2 Deadline

11. 11 of 14 11/15 Motivational Example #3 P1P1 N1N1 P4P4 TTP S1S1 T CAN N2N2 P2P2 NGNG SGSG m1m1 SGSG S1S1 T m2m2 T P3P3 T S1S1 SGSG m4m4 S1S1 SGSG m3m3 Round 4 Missed m1m1 m3m3 m2m2 m4m4 What are the priorities on ETC? Which slot should come first on the TTC? P1P1 P2P2 P3P3 P4P4 N1N1 N2N2 20X X X 40 X 20 P1P1 P4P4 P2P2 P3P3 m1m1 m2m2 m3m3 m4m4 N1N1 N2N2 TTC CAN TTP ETC P1P1 N1N1 P4P4 TTP S1S1 T CAN N2N2 P2P2 NGNG SGSG m1m1 SGSG S1S1 T m2m2 T P3P3 T S1S1 SGSG SGSG Missed m1m1 m2m2 m3m3 m4m4 m3m3 m4m4 P1P1 N1N1 P4P4 TTP SGSG T CAN N2N2 P2P2 NGNG S1S1 TT P3P3 S1S1 SGSG S1S1 SGSG m4m4 m3m3 Met Round 1 m2m2 m1m1 m4m4 m3m3 m1m1 m2m2 Deadline

12. 12 of 14 12/15 Optimization Strategy  Multi-Cluster Configuration 1.Initial Partitioninig and Mapping  Determines an initial partitioning and mapping  List scheduling-based greedy approach  Priority of ready processes: critical path 2.Partitioning and Mapping Heuristic  Iteratively improves on the initial partitioning and mapping  Intelligent design transformations that improve schedulability  Based on feedback from MultiClusterScheduling 3.Bus Access Optimization  Determines the slot sequence and lengths on the TTC, message priorities on the ETC  Greedy optimization heuristic  Straightforward solution  Partitioning and mapping that balances the utilization of processors and buses  Could be produced by a designer without optimzation tools

13. 13 of 14 13/15 Experimental Results 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 50100150200250 Percentage schedulable applications [%] Number of processes Can we increase the number of schedulable applications? Straightforward solution Bus Access Optimization Partitioning and Mapping Heuristic Initial Partitioning and Mapping

14. 14 of 14 14/15 Experimental Results, Cont. How time-consuming is our optimization strategy? 0:00 0:20 0:40 1:00 1:20 1:40 2:00 2:20 2:40 3:00 3:20 3:40 4:00 4:20 4:40 5:00 5:20 50100150200250 Average execution time [hours:minutes] Number of processes Multi-Cluster Configuration Partitioning and Mapping Heuristic Initial Partitioning and Mapping Bus Access Optimization  Case study  Vehicle cruise controller  Distributed over the TT and ET clusters

15. 15 of 14 15/15 Contributions and Message  Contributions  Addressed design problems characteristic to multi-clusters  Partitioning  Mapping  Bus Access Optimization  Proposed heuristics for design optimization Analysis and optimization methods are needed for the efficient implementation of applications distributed over interconnected heterogeneous networks.