1. A Defect Tolerant and Performance Tunable Gate Architecture for End-of-Roadmap CMOS Adit D. Singh Electrical and Computer Engineering, Auburn University AL 36849 National Science Foundation CNS 0708962 and CCF0811454

2. 2 Motivation  No visibility on technology beyond CMOS  CMOS appears here to stay!  Scaling projected to continue  At least a decade of design likely in nano- scale “End-of-Roadmap” CMOS

3. 3 End-of-Roadmap CMOS Characterized by  Atomic scale feature sizes (~100 Si atoms in 45nm)  Physical limits in material properties  Random dopant fluctuations  Extreme sub-wavelength lithography Potential for  High manufacturing defectivity  Operational wear out & degradation  Highy random performance variation

4. 4 End-of-Roadmap CMOS Characterized by  Atomic scale feature sizes  Physical limits in material properties  Random dopant fluctuations  Extreme sub-wavelength lithography Potential for  High manufacturing defectivity  Operational wear out & degradation  Highly random performance variation Defect Tolerance Performance Tuning

5. Clock Speed and Parameter Variation  Clock rate determined by slowest path  Manufacturing variability forces different clock rates: “Speed Binning”  Speed Binning works for systematic variability  Less effective for random variability Comb. Logic FF Clock

6. Speed Binning Traditional Systematic Variability  Device parameters track within a chip within a chip  All gates slow or all fast  Some chips slow, some fast fast  Average clock rate over many manufactured parts many manufactured parts = clock rate for average = clock rate for average parameter values parameter values FF Clock

7. Random Variability  Random parameter variability within chip  Every copy of a large circuit highly likely to have a few very slow paths  Average clock frequency << clock rate for average << clock rate for average parameter values parameter values (for large circuits) (for large circuits) FF Clock

8. Random Variability Statistical: 1 in 100 very slow gate 18 gate design 150 gate design A few slow parts Virtually all slow parts

9. 9 Normal Distribution

10. Random Variability: Speed Vs Size  Large circuits statistically more likely to have one or more slow outlier paths FF Clock 1 10 100 1000 10000 (log scale) Circuit Size Average worst case path delay worst case path delay

11. Post Manufacture Performance Tuning “Delay Fault Tolerance”  Capability to allow speed-up of statistically slow outlier paths FF Clock 1 10 100 1000 10000 (log scale) Circuit Size Average worst case path delay worst case path delay GOAL

12. 12 Defect Tolerant & Tunable CMOS P-Net N-Net Sized and Programmable Sized and Programmable Switch Programmable Switch

13. 13 Defect Free Operation P-Net N-Net Sized and Programmable Sized and Programmable ON OFF ON Traditional CMOS

14. 14 Defect in P-Net P-Net N-Net OFF ON  Pseudo nMOS operation  Pull-up sized for ratio logic  R pu ~ 4 R pd

15. 15 Defect in N-Net P-Net N-Net OFF ON  Pseudo PMOS operation  Pull-down sized for ratio logic  R pd ~ 4 R pu

16. 16 Performance Tuning: Slow P-transistor P-Net N-Net ON OFF  Redundant PMOS speeds up rising transitions  Speed up greatest for very slow outlier transistor  Some slow down of opposite falling transitions 

17. 17 Performance Tuning: Slow P-transistor P-Net N-Net ON OFF Assume nominal Rpu = Rpd and R_tuning = 4 Rpd Defective Extra Delay Rpu Untuned Tune d 1.5X 0.5X 0.10X 2X 1X 0.33X 4X 3X 1.00X 6X 5X 1.40X 8X 7X 2.20X 1X 0X - 0.2X Speedup

18. 18 Performance Tuning: Slow P-transistor P-Net N-Net ON OFF Assume nominal Rpu = Rpd and R_tuning = 4 Rpd Defective Extra Delay Rpu Untuned Tune d 1.5X 0.5X 0.10X 2X 1X 0.33X 4X 3X 1.00X 6X 5X 1.40X 8X 7X 2.20X 1X 0X - 0.2X Speedup

19. 19 Performance Tuning: Slow P-transistor Defective Extra Delay Rpu Untuned Tune d 1.5X 0.5X 0.10X 2X 1X 0.33X 4X 3X 1.00X 6X 5X 1.40X 8X 7X 2.20X 1X 0X - 0.2X Assume 10 level path Untuned delay = 13X Tuned Delay = 11 X Tuning 2 additional gates: Tuned Delay = 10.6X Speedup

20. 20 Simulation Experiments  Simplified simulation of inverter chains  Transistor parameters drawn from a Normal Distribution - different variance values  Circuit size measured by number of chains  For each “circuit” worst case untuned and tuned delays obtained.

21. Post Manufacture Performance Tuning “Delay Fault Tolerance”  Simulate and average over a large number of instances for each “circuit” size FF Clock 1 10 100 1000 10000 (log scale) Circuit Size Average worst case path delay worst case path delay GOAL

22. Observed Delay Variations Tuned and Untuned 22 10 1 10 2 10 3 10 4 10 5 1.9 x 10 -10 2.7 2.6 2.5 2.4 2.3 2.2 2.0 2.1 Delay (sec) Standard Deviation = 1/6 mean 8 stage inverter chains 20%

23. Observed Delay Variations for different sigmas 23 10 4 10 1 10 3 10 2 1 1 2 3 7 4 5 6 10 9 8 Delay (sec) Number of circuits(log scale) x 10 -10

24. 24 Defect Tolerant & Tunable CMOS Gate P-Net N-Net Sized and Programmable Sized and Programmable Switch Programmable Switch Conclusion End-of-Roadmap Applications