1. DARPA Simulation and Synthesis of Quantum Circuits Igor L. Markov and John P. Hayes Advanced Computer Architecture Laboratory University of Michigan, EECS

2. DARPA Quantum Circuits Group @UMich PIs: Prof. Igor Markov & Prof. John Hayes PIs: Prof. Igor Markov & Prof. John Hayes Postdoc: Dr. Ketan Patel (circuit testing) Postdoc: Dr. Ketan Patel (circuit testing) Graduate Student Researchers & Fellows Graduate Student Researchers & Fellows George Viamontes (simulation/QuIDDs) George Viamontes (simulation/QuIDDs) Manoj Rajagopalan (simulation, synthesis by SA) Manoj Rajagopalan (simulation, synthesis by SA) DoRon Motter (circuit complexity) DoRon Motter (circuit complexity) Smita Krishnaswamy (quantum clocks) Smita Krishnaswamy (quantum clocks) Parmoon Seddighrad (technology-specific opt.) Parmoon Seddighrad (technology-specific opt.)

3. DARPA High-level Assumptions and Goals Assumption: physicists [will] have “promising” technology prototypes Assumption: physicists [will] have “promising” technology prototypes Expectation: at 20+ qubits, design complexity becomes a serious issue Expectation: at 20+ qubits, design complexity becomes a serious issue Even at 20 bits, optimal logic synthesis is difficult Even at 20 bits, optimal logic synthesis is difficult Our job: improve the competitiveness of prototypes and facilitate applications Our job: improve the competitiveness of prototypes and facilitate applications Address specific design objectives and trade-offs Address specific design objectives and trade-offs Discover scalable design/simulation techniques Discover scalable design/simulation techniques Connect design techniques with applications Connect design techniques with applications Id new types of q. circuits and new applications Id new types of q. circuits and new applications

4. DARPA Our Expertise Computer Architecture Computer Architecture Electronic Design Automation / VLSI CAD Electronic Design Automation / VLSI CAD Automated Synthesis of Logic Circuits Automated Synthesis of Logic Circuits Formal Verification Formal Verification Circuit Layout Circuit Layout Circuit Testing Circuit Testing Design & analysis of algorithms/heuristics Design & analysis of algorithms/heuristics Including Algorithm Engineering (implementation, evaluation, integration) Including Algorithm Engineering (implementation, evaluation, integration)

5. DARPA Design Productivity Gap NTRS / ITRS: Design Productivity Gap is roughly 49% a year vs 21% a year NTRS / ITRS: Design Productivity Gap is roughly 49% a year vs 21% a year Is “quantum D. P. G.” looming ? Is “quantum D. P. G.” looming ?

6. DARPA Fundamental Optimizations Research in Design Automation targets core computational obstacles Research in Design Automation targets core computational obstacles E.g., scalability in terms of runtime & QOR E.g., scalability in terms of runtime & QOR Value in trying to solve “wrong” problems Value in trying to solve “wrong” problems Many optimization algorithms can be easily “re-focused” Many optimization algorithms can be easily “re-focused” Different objectives and constraints Different objectives and constraints Example: Simulated Annealing Example: Simulated Annealing

7. DARPA Research Themes (1) “From classical to quantum” “From classical to quantum” Use classical reversible circuits as [simple] test-bed Use classical reversible circuits as [simple] test-bed Leverage and generalize known design techniques for classical circuits Leverage and generalize known design techniques for classical circuits Simulation-driven design Simulation-driven design Support for quantum circuit testing Support for quantum circuit testing Ability to incrementally improve designs based on results of simulations/tests Ability to incrementally improve designs based on results of simulations/tests Ability to empirically evaluate quantum designs and algorithms without easily-provable properties Ability to empirically evaluate quantum designs and algorithms without easily-provable properties

8. DARPA Research Themes (2) New types of quantum circuits New types of quantum circuits Case-by-case automatic synthesis versus asymptotic constructions Case-by-case automatic synthesis versus asymptotic constructions “Real life” vs theory (cf. synthesis of classical random logic) “Real life” vs theory (cf. synthesis of classical random logic) Empirical performance versus provable results Empirical performance versus provable results Separate design and simulation/test stages Separate design and simulation/test stages Example: sequential versus combinational Example: sequential versus combinational New applications New applications Enabled by automatic synthesis Enabled by automatic synthesis Leveraging new types of circuits, e.g., sequential Leveraging new types of circuits, e.g., sequential

9. DARPA Research Topics (1) Synthesis algorithms for classical logic as subroutines for quantum circuit synthesis Synthesis algorithms for classical logic as subroutines for quantum circuit synthesis Algebraic approaches to circuit synthesis Algebraic approaches to circuit synthesis E.g., abstract and computational group theory E.g., abstract and computational group theory Matrix factorizations: QR, ILU, CS and KAK Matrix factorizations: QR, ILU, CS and KAK Special-case synthesis, e.g., Grover oracles Special-case synthesis, e.g., Grover oracles Generic quantum circuit synthesis and reduction Generic quantum circuit synthesis and reduction Dynamic programming Dynamic programming Annealing and other heuristics Annealing and other heuristics

10. DARPA Research Topics (2) Automatic error correction during synthesis Automatic error correction during synthesis Efficient simulation of quantum circuits Efficient simulation of quantum circuits Graph-theoretical algorithms based on common arithmetic sub-expressions (QUIDDs) Graph-theoretical algorithms based on common arithmetic sub-expressions (QUIDDs) New types of quantum circuits New types of quantum circuits Quantum clocks and other sequential circuits Quantum clocks and other sequential circuits New [and old] applications New [and old] applications Quantum optimization algorithms (heuristics) Quantum optimization algorithms (heuristics) Memory-savvy versions of known algorithms Memory-savvy versions of known algorithms

11. DARPA Remaining Part Of The Talk Synthesis of Reversible Logic Circuits and Applications to Grover’s Search Synthesis of Reversible Logic Circuits and Applications to Grover’s Search Synthesis of Quantum Circuits by Simulated Annealing Synthesis of Quantum Circuits by Simulated Annealing High-performance Simulation of Quantum Circuits using QuIDDs High-performance Simulation of Quantum Circuits using QuIDDs

12. DARPA Optimal Synthesis of Reversible Logic Circuits Vivek V. Shende, Aditya K. Prasad, Igor L. Markov and John P. Hayes Advanced Computer Architecture Laboratory University of Michigan, EECS

13. DARPA Outline Motivation Motivation Real-world Applications Real-world Applications Asymptotically Zero-Energy circuits Asymptotically Zero-Energy circuits Links to Quantum Computation Links to Quantum Computation Background Background Theoretical Results Theoretical Results Synthesis of Optimal Circuits Synthesis of Optimal Circuits An Application to Quantum Computing An Application to Quantum Computing

14. DARPA Real-world Applications Many inherently reversible applications Many inherently reversible applications Info. is re-coded, but none is lost or added Info. is re-coded, but none is lost or added Digital signal processing Digital signal processing Cryptography Cryptography Communications Communications Computer graphics Computer graphics Network congestion modeling Network congestion modeling

15. DARPA Links to Quantum Computation Quantum operations are all reversible Quantum operations are all reversible Every (classical) reversible circuit may be implemented in quantum technology, with overhead Every (classical) reversible circuit may be implemented in quantum technology, with overhead “Pseudo-classical” subroutines of quantum algos “Pseudo-classical” subroutines of quantum algos Can be implemented in classical reversible logic circuits Can be implemented in classical reversible logic circuits Grover’s search : Grover’s search :

16. DARPA Outline Motivation Motivation Background Background Reversibility Reversibility Permutations Permutations Known Facts Known Facts Theoretical Results Theoretical Results Synthesis of Optimal Circuits Synthesis of Optimal Circuits An Application to Quantum Computing An Application to Quantum Computing

17. DARPA Reversibility in Logic Gates Definition: reversible logic gate Definition: reversible logic gate #input wires = #output wires #input wires = #output wires Permutes the set of input values Permutes the set of input values Examples Examples Inverter Inverter 2-input, 2-output SWAP (S) gate 2-input, 2-output SWAP (S) gate k-CNOT gate k-CNOT gate (k+1)-inputs and (k+1)-outputs (k+1)-inputs and (k+1)-outputs Values on the first k wires are unchanged Values on the first k wires are unchanged The last value is flipped if the first k were all 1 The last value is flipped if the first k were all 1

18. DARPA Reversibility in Logic Circuits Definition: A combinational logic circuit is reversible iff Definition: A combinational logic circuit is reversible iff It contains only reversible gates It contains only reversible gates It has no fan-out It has no fan-out It is acyclic as a directed multi-graph It is acyclic as a directed multi-graph Theorem: A reversible circuit must Theorem: A reversible circuit must Have as many input wires as output wires Have as many input wires as output wires Permute the set of input values Permute the set of input values

19. DARPA A Reversible Circuit and Truth Table xyzx’y’z’ 000000 001001 010011 011010 100100 101101 110111 111110 Equivalent to a single CNOT gate

20. DARPA Circuit Equivalences Circuit equivalences: useful in synthesis More will be shown later

21. DARPA Reversible Circuits & Permutations A reversible gate (or circuit) with n inputs and n outputs has A reversible gate (or circuit) with n inputs and n outputs has 2 n possible input values 2 n possible input values 2 n possible output values 2 n possible output values The function it computes on this set must, by definition, be a permutation The function it computes on this set must, by definition, be a permutation The set of such permutations is called S 2 n The set of such permutations is called S 2 n

22. DARPA Basic Facts About Permutations Permutations are multiplied by first applying one, then the other Permutations are multiplied by first applying one, then the other example: (1,2)◦(2,3) = (1,3,2) example: (1,2)◦(2,3) = (1,3,2) A transposition A transposition permutes exactly two elements permutes exactly two elements does not change any others does not change any others Every permutation can be written as a product of transpositions Every permutation can be written as a product of transpositions

23. DARPA Even Permutations Consider all possible decompositions of a permutation into transpositions Consider all possible decompositions of a permutation into transpositions Theorem: The parity of the number of transpositions is constant Theorem: The parity of the number of transpositions is constant Definition: Even permutations are those for which the number of transpositions is even Definition: Even permutations are those for which the number of transpositions is even

24. DARPA Known Facts Fact 1: Consider a reversible circuit Fact 1: Consider a reversible circuit n+1 inputs and n+1 outputs n+1 inputs and n+1 outputs Built from gates which have at most n inputs and n outputs Built from gates which have at most n inputs and n outputs Must compute an even permutation Must compute an even permutation Fact 2: A universal gate library Fact 2: A universal gate library CNOT, NOT, and TOFFOLI (“CNT”) CNOT, NOT, and TOFFOLI (“CNT”) Temporary storage may be required Temporary storage may be required

25. DARPA Temporary Storage

26. DARPA Outline Motivation Motivation Background Background Theoretical Results Theoretical Results Zero-storage Circuits Zero-storage Circuits Reversible De Morgan’s Laws Reversible De Morgan’s Laws Synthesis of Optimal Circuits Synthesis of Optimal Circuits An Application to Quantum Computing An Application to Quantum Computing

27. DARPA Minimizing Temporary Storage Consider CNT circuits Consider CNT circuits Theorem: even permutations computable by circuits without temporary storage Theorem: even permutations computable by circuits without temporary storage Theorem: odd permutations computable with one line of temporary storage Theorem: odd permutations computable with one line of temporary storage Same holds for NT and CNTS circuits Same holds for NT and CNTS circuits The proof is constructive and may be used as a synthesis heuristic The proof is constructive and may be used as a synthesis heuristic

28. DARPA Outline of Proof Explicitly construct a circuit to compute an arbitrary pair of disjoint transpositions (A, B) (C, D) is okay; (A, B) (B, C) is not Explicitly construct a circuit to compute an arbitrary pair of disjoint transpositions (A, B) (C, D) is okay; (A, B) (B, C) is not Pick an even permutation Pick an even permutation Decompose it into transpositions Decompose it into transpositions Will have an even number of transpositions Will have an even number of transpositions Pair these up, guaranteeing disjointness Pair these up, guaranteeing disjointness Apply construction to each pair Apply construction to each pair

29. DARPA Flowchart of Proof

30. DARPA Reversible De Morgan’s Laws (1) De Morgan’s Laws De Morgan’s Laws Can send inverters to inputs in AND/OR/NOT circuits Can send inverters to inputs in AND/OR/NOT circuits Reversible De Morgan’s Laws Reversible De Morgan’s Laws Can send inverters to inputs in CNT circuits Can send inverters to inputs in CNT circuits Rules exist to move TOFFOLI and CNOT gates Rules exist to move TOFFOLI and CNOT gates However, it is not always possible to push all CNOT gates to the inputs However, it is not always possible to push all CNOT gates to the inputs Oddly enough, all CNOT gates can be pushed to the “middle” of the circuit Oddly enough, all CNOT gates can be pushed to the “middle” of the circuit

31. DARPA Reversible De Morgan’s Laws (2)

32. DARPA Reversible De Morgan’s Laws (3)

33. DARPA Outline Motivation Motivation Background Background Theoretical Results Theoretical Results Synthesis of Optimal Circuits Synthesis of Optimal Circuits Optimality Optimality DFID Search Algorithm DFID Search Algorithm Circuit Libraries Circuit Libraries An Application to Quantum Computing An Application to Quantum Computing

34. DARPA Optimality The cost of a circuit is its gate count The cost of a circuit is its gate count Other cost functions can be considered Other cost functions can be considered Definition: optimal reversible circuit Definition: optimal reversible circuit no circuit with fewer gates computes the same permutation no circuit with fewer gates computes the same permutation Theorem: a sub-circuit of an optimal circuit is optimal Theorem: a sub-circuit of an optimal circuit is optimal Proof: otherwise, can improve the sub-circuit Proof: otherwise, can improve the sub-circuit

35. DARPA The Search Procedure Depth First Iterative Deepening Search Depth First Iterative Deepening Search Checks all possible circuits of cost 1, then all possible circuits of cost 2, etc… Checks all possible circuits of cost 1, then all possible circuits of cost 2, etc… Avoids the memory blowup of BFS Avoids the memory blowup of BFS Still finds optimal solutions (unlike DFS) Still finds optimal solutions (unlike DFS) Checking circuits of cost less than n is much faster than processing cost-n circuits Checking circuits of cost less than n is much faster than processing cost-n circuits

36. DARPA Dynamic Prog + Circuit Libraries DFID search requires a subroutine to check all circuits of cost n, for arbitrary n DFID search requires a subroutine to check all circuits of cost n, for arbitrary n Called iteratively for 1…n Called iteratively for 1…n Only need to check locally optimal circuits Only need to check locally optimal circuits Build optimal circuit library bottom up by DP Build optimal circuit library bottom up by DP Index optimal circuits by computed permutation Index optimal circuits by computed permutation In practice use hash_map datastruct from STL In practice use hash_map datastruct from STL

37. DARPA Synthesis Algorithm

38. DARPA Empirical Circuit Synthesis Consider all reversible functions on 3 wires (8! = 40,320 functions) Consider all reversible functions on 3 wires (8! = 40,320 functions) For each gate library from N, C, T, NC, CT, NT, CNT, CNTS For each gate library from N, C, T, NC, CT, NT, CNT, CNTS Is it universal? Is it universal? How many functions can it synthesize? How many functions can it synthesize? How long does it take to synthesize circuits? How long does it take to synthesize circuits? What are largest optimal circuits? What are largest optimal circuits?

39. DARPA Optimal Circuit Sizes SizeNCTNCCTNTCNTCNTS 12000004700 1100000169000 1000000836300 9000001223700 800006933957732 7000143865097102536817 6020215168822621704917531 502404741784870892111194 4060539384529627803752 3151918726188625844 23246516024102135 13639961215 011111111 Total8168241344504040320 Time, s11130215974015

40. DARPA Largest Optimal Circuits Note that purely quantum gates can enable smaller circuits Note that purely quantum gates can enable smaller circuits John A. Smolin, "Five two-bit quantum gates are sufficient to implement the quantum Fredkin gate“, PRA 53(4), 1996, pp. 2855-2856 John A. Smolin, "Five two-bit quantum gates are sufficient to implement the quantum Fredkin gate“, PRA 53(4), 1996, pp. 2855-2856 Q. Circuit Synthesis via the Ring Normal Form (papers by Thomas Beth and Martin Röttler) Q. Circuit Synthesis via the Ring Normal Form (papers by Thomas Beth and Martin Röttler)

41. DARPA Why Circuit Libraries? Large speedup over straight DFID Large speedup over straight DFID Can be calculated from previous table Can be calculated from previous table Calculated values are very large Calculated values are very large In practice, the table cannot be generated in several hours without circuit libraries In practice, the table cannot be generated in several hours without circuit libraries With libraries, the table takes less than 10 min With libraries, the table takes less than 10 min

42. DARPA Outline Motivation Motivation Background Background Theoretical Results Theoretical Results Synthesis of Optimal Circuits Synthesis of Optimal Circuits An Application to Quantum Computing An Application to Quantum Computing Grover’s Search Grover’s Search Pseudo-classical Synthesis Pseudo-classical Synthesis

43. DARPA Quantum Circuits Necessarily reversible Necessarily reversible Bit-lines are now qubits Bit-lines are now qubits All classical reversible gates still allowed All classical reversible gates still allowed Many other gates used as well Many other gates used as well Circuit equivalences for reversible gates are still valid ! Circuit equivalences for reversible gates are still valid !

44. DARPA Grover’s Search A quantum algorithm for associative search (input is not sorted) A quantum algorithm for associative search (input is not sorted) Search criterion: a classical one-output function f Search criterion: a classical one-output function f Runs in time O(√N) Runs in time O(√N) classical algorithms require  (N ) time classical algorithms require  (N ) time Requires a subroutine that Requires a subroutine that changes the phase (sign) of all basis states (bit-strings) that match the search criterion f changes the phase (sign) of all basis states (bit-strings) that match the search criterion f

45. DARPA Grover Oracle Circuits To change the sign of a bit-string To change the sign of a bit-string Initialize a qubit to |0> - |1> Initialize a qubit to |0> - |1> Compute the classical one-output function f Compute the classical one-output function f XOR the qubit with f XOR the qubit with f Whenever f =1, the sign (phase) will change Whenever f =1, the sign (phase) will change Thus, the design of Grover search circuits for a given f Thus, the design of Grover search circuits for a given f Is reduced to reversible synthesis Is reduced to reversible synthesis Can be solved optimally by our methods Can be solved optimally by our methods

46. DARPA Sample Grover Circuit

47. DARPA ROM-based Circuits Desired circuits must alter phase of basis states Desired circuits must alter phase of basis states All bits except one must be restored to input values All bits except one must be restored to input values Previous work studied ROM-based circuits Previous work studied ROM-based circuits Constraint: ROM qubits can never change Constraint: ROM qubits can never change B. Travaglione et al., 2001, http://xxx.lanl.gov/abs/quant-ph/0109016 B. Travaglione et al., 2001, http://xxx.lanl.gov/abs/quant-ph/0109016 Theorems + heuristic synthesis algorithms Theorems + heuristic synthesis algorithms Our work: synthesis of pseudo-classical circuits Our work: synthesis of pseudo-classical circuits 3 read-only “ROM” wires that can never change 3 read-only “ROM” wires that can never change 1 wire that can be changed during computation, but must be restored by end 1 wire that can be changed during computation, but must be restored by end 1 wire on which function is computed 1 wire on which function is computed

48. DARPA Synthesis Algorithms Compared Heuristic synthesis of ROM-based circuits Heuristic synthesis of ROM-based circuits Proposed by Travaglione et al, 2001 Proposed by Travaglione et al, 2001 Based on XOR-sum decomposition (“XOR”) Based on XOR-sum decomposition (“XOR”) Imposed a restriction: at most one control bit per gate can be on a ROM bit Imposed a restriction: at most one control bit per gate can be on a ROM bit Optimal synthesis (as described earlier) Optimal synthesis (as described earlier) with restriction from Travaglione (“OPT T”) with restriction from Travaglione (“OPT T”) without this restriction (“OPT”) without this restriction (“OPT”)

49. DARPA Sizes of 3+2 ROM-circuits Size0123456789101112 XOR146441218126 191610 OPT T146441221242933444622 OPT1721353628 363521710 Size1314151617181920212223 2425 26 XOR8101619126 1812446 4 1 OPT T510000000000 0 0 OPT000000000000 0 0

50. DARPA Discussion of Empirical Results The XOR-SUM heuristic is sub-optimal The XOR-SUM heuristic is sub-optimal All methods able to synthesize all 256 fns All methods able to synthesize all 256 fns “OPT T” can synthesize as many as “OPT”: “OPT T” can synthesize as many as “OPT”: B. Travaglione et al., 2001 B. Travaglione et al., 2001 “OPT” results symmetrical about 5-6 gates “OPT” results symmetrical about 5-6 gates Function x requires one fewer gate than 256-x Function x requires one fewer gate than 256-x Explanation yet to be found Explanation yet to be found “XOR” results symmetrical about 13 gates “XOR” results symmetrical about 13 gates

51. DARPA Conclusions Classical reversible circuits as special-case quantum circuits Classical reversible circuits as special-case quantum circuits Existence theorems Existence theorems Reversible De Morgan’s laws Reversible De Morgan’s laws Future research on optimization heuristics Future research on optimization heuristics Algorithm for synthesis of optimal circuits Algorithm for synthesis of optimal circuits Applicable to Grover’s search Applicable to Grover’s search See details in quant-ph/0207011 See details in quant-ph/0207011 A more detailed version will posted by 09/22 A more detailed version will posted by 09/22

52. DARPA Quantum Circuit Synthesis by Simulated Annealing Manoj Rajagopalan, Igor L. Markov, and John P. Hayes Advanced Computer Architecture Laboratory University of Michigan, EECS

53. DARPA The Problem Synthesize a quantum circuit Synthesize a quantum circuit Using gates from the given library Using gates from the given library To achieve a specified unitary matrix (can also consider effects of measurement) To achieve a specified unitary matrix (can also consider effects of measurement) Very few qubits are considered Very few qubits are considered All matrices are still very small All matrices are still very small Yet, there can be many of gates Yet, there can be many of gates

54. DARPA Synthesis Techniques Exhaustive Search Exhaustive Search Matrix Factorization (QR, CS, ILU,KAK) Matrix Factorization (QR, CS, ILU,KAK) [Cybenko2000] uses QR [Cybenko2000] uses QR Dynamic Programming + Branch & Bound Dynamic Programming + Branch & Bound [ShendePMH2002], quant-ph/0207001 [ShendePMH2002], quant-ph/0207001 Genetic Algorithms Genetic Algorithms [WilliamsG1999, YabukiI2001] [WilliamsG1999, YabukiI2001] Simulated Annealing: this work Simulated Annealing: this work

55. DARPA Simulated Annealing Stochastic algorithm Stochastic algorithm form of local search for solving optimization problems form of local search for solving optimization problems Annealing: heating and gradual cooling to toughen (metal or glass) and reduce brittleness Annealing: heating and gradual cooling to toughen (metal or glass) and reduce brittleness Simulated annealing (combinatorial optimization) Simulated annealing (combinatorial optimization) Objective function ~ energy of system Objective function ~ energy of system Minimized by simulating Brownian motion with decreasing temperature Minimized by simulating Brownian motion with decreasing temperature Moves randomly selected, good ones accepted, and bad ones accepted in some cases Moves randomly selected, good ones accepted, and bad ones accepted in some cases Probability of accepting bad move = e (-  cost / T) Probability of accepting bad move = e (-  cost / T)

56. DARPA Simulated Annealing for Q.S. Represent circuit synthesis as an optimization problem Represent circuit synthesis as an optimization problem Solution space: Solution space: Quantum circuits (circuit topology + gate types) Quantum circuits (circuit topology + gate types) Constraints: Constraints: Output must match specification for given input Output must match specification for given input Gates from given library Gates from given library Objectives: Objectives: Minimize number of gates Minimize number of gates Minimize the error (in some norm) Minimize the error (in some norm)

57. DARPA A Naive Annealer + Extension Consider individual circuits, one at a time Consider individual circuits, one at a time Evaluate matrix product of all gates Evaluate matrix product of all gates Compute the error Compute the error Better idea: incremental evaluation Better idea: incremental evaluation Add/remove/change one gate at a time Add/remove/change one gate at a time Incrementally compute matrix product Incrementally compute matrix product

58. DARPA Incremental Perturbation Perturb gates at ends of circuit Perturb gates at ends of circuit Effect of adding and removing single gates realized by qubit-wise multiplication Effect of adding and removing single gates realized by qubit-wise multiplication Asymptotic improvement per move Asymptotic improvement per move Suppose we have N gates Suppose we have N gates Incremental evaluation: O(1) time Incremental evaluation: O(1) time Evaluation from scratch: O(N) time Evaluation from scratch: O(N) time

59. DARPA Simulated Annealing Procedure Initial solution: empty circuit (Id matrix) Initial solution: empty circuit (Id matrix) Choose initial temperature (…), final T = 0 Choose initial temperature (…), final T = 0 Adopt a temp. schedule (linear, geometric) Adopt a temp. schedule (linear, geometric) Single-qubit move and CNOT moves Single-qubit move and CNOT moves At either end of current circuit, select (with equal probability) from At either end of current circuit, select (with equal probability) from No change (NOP) No change (NOP) Add a gate (ADD) Add a gate (ADD) Remove a gate (REM) Remove a gate (REM) Replace a gate (REP) Replace a gate (REP)

60. DARPA Simulated Annealing Procedure Make a random move Make a random move Evaluate error of new circuit Evaluate error of new circuit If error <10 -6, consider synthesis complete If error <10 -6, consider synthesis complete Else evaluate cost: weighted sum of error and #gates Else evaluate cost: weighted sum of error and #gates If a move improves cost, then accept it If a move improves cost, then accept it Else accept move with probability exp (-  cost / T) Else accept move with probability exp (-  cost / T) Must accept some bad moves to avoid local minima Must accept some bad moves to avoid local minima T=0 means greedy T=0 means greedy Low-temperature annealing cannot climb hills well Low-temperature annealing cannot climb hills well

61. DARPA Simulated Annealing Procedure Reduce temp. according to schedule Reduce temp. according to schedule Repeat move selection, acceptance… Repeat move selection, acceptance… Perform iterations until final temperature is reached Perform iterations until final temperature is reached

62. DARPA Implementation Platform AMD Athlon 1.2 GHz processor AMD Athlon 1.2 GHz processor Debian Linux Debian Linux C++ (g++ v2.95.4 –O3) C++ (g++ v2.95.4 –O3)

63. DARPA Quantum Gates

64. DARPA Test 1: H-X-Z gate circuits Hadamard (H), Not (X) and Phase shift (Z) Hadamard (H), Not (X) and Phase shift (Z) Optimal one-qubit circuits typically require up to 3 gates per qubit Optimal one-qubit circuits typically require up to 3 gates per qubit Targets for synthesis: Targets for synthesis: randomly generated circuits with 5 qubits randomly generated circuits with 5 qubits Results averaged over 100 independent starts Results averaged over 100 independent starts

65. DARPA H-X-Z circuit results (5 qubits) Library Min Size (# gates) Avg Size (# gates) Avg Time (s) Success rate H X Z 6170.60 100 % H X Z ½ 7275.53 82 % H Z 8231.82 99 % H X 10523.48 81 % H Z ½ 12294.23 81 %

66. DARPA H-X-Z circuit results Reasonably small runtimes Reasonably small runtimes Near-optimal (?) circuits found Near-optimal (?) circuits found We were not able to find better circuits by paper & pencil calculations We were not able to find better circuits by paper & pencil calculations In principle, can change the gate library In principle, can change the gate library

67. DARPA Test 2: Teleportation circuits ([WilliamsG1999] & [YabukiI2001] R L S T S SenderReceiver Circuits with CNOT gates

68. DARPA Quantum Gates R = Z H = H X L = H Z = X H R = L † S = X Z ½ X

69. DARPA Synthesis of Sender-Circuit GateLibrary Min Size (# gates) Avg Size (# gates) Avg Time (s) Success Rate L,CNOT,R45311.23 95 % CNOT,H, X 2012531.43 51 % CNOT,H,Z816238.4645%

70. DARPA Receiver Circuit Synthesis GateLibrary Min Size (# gates) Avg Size (# gates) Avg Time (s) Success Rate S,CNOT,T450.05 100 % (83% opt) H,CNOT,Z ½ 460.11 100 % (68% opt) H,CNOT,Z ½ Z ¼, X 350.22 100 % (44% opt)

71. DARPA Teleportation: Previous Work Williams and Gray (Genetic Algos) Williams and Gray (Genetic Algos) Both circuits with 4 gates, 100% success rate Both circuits with 4 gates, 100% success rate Initial population size is 100 circuits Initial population size is 100 circuits Requires 4 generations - 2640 circuit evaluations - on average Requires 4 generations - 2640 circuit evaluations - on average Yabuki and Iba (Genetic Algos) Yabuki and Iba (Genetic Algos) Sender circuit - 4 gates, Receiver - 3 gates Sender circuit - 4 gates, Receiver - 3 gates Simplify the problem by exploiting features Simplify the problem by exploiting features Requires 350 generations of 5000 candidates on average Requires 350 generations of 5000 candidates on average

72. DARPA Conclusions Simulated annealing Simulated annealing Promising heuristic for synthesis of q. circuits Promising heuristic for synthesis of q. circuits Benefits from incremental evaluation Benefits from incremental evaluation Reasonably fast Reasonably fast Competitive with Genetic Algorithms (better?) Competitive with Genetic Algorithms (better?) Flexibility Flexibility Gate libraries can be easily changed (e.g., over-specified) Gate libraries can be easily changed (e.g., over-specified) Various optim. objectives can be addressed Various optim. objectives can be addressed Ditto for constraints Ditto for constraints

73. DARPA On-going Work More focus on minimizing the number of gates More focus on minimizing the number of gates So far, mostly tried to find a circuit quickly So far, mostly tried to find a circuit quickly Account for more physical phenomena Account for more physical phenomena Circuit equivalence up to global phase Circuit equivalence up to global phase Adaptive move-type selection Adaptive move-type selection Based on how successful previous moves were Based on how successful previous moves were Temperature schedule, initial temperature Temperature schedule, initial temperature More challenging synthesis problems More challenging synthesis problems Add Toffoli gates (increased inter-qubit interaction) Add Toffoli gates (increased inter-qubit interaction) Continuous gate libraries (single-paramater gates) Continuous gate libraries (single-paramater gates)

74. DARPA References 1. G.Cybenko, “Reducing quantum computations to elementary unitary operations”, Comp. in Sci. and Engin., pp.27-32, March/April 2001. 2. V.V.Shende, A.K.Prasad, I.L.Markov, J.P.Hayes, “Reversible Logic Circuit Synthesis”, to appear in Proc. ACM/IEEE Intl. Conf. Comp.-Aided Design, Nov. 2002 3. C.P.Williams, A.G.Gray “Automated design of quantum circuits”, In QCQC’98 LNCS 1509, pp. 113-125, Springer-Verlag, 1999. 4. T.Yabuki, H.Iba, “Genetic Algorithms for quantum circuit design –Evolving a simpler teleportation circuit-”, In Late Breaking Papers at the 2000 Genetic and Evolutionary Computation Conf., Las Vegas, NV, pp. 425-430, 2000.

75. DARPA High-Performance Simulation of Quantum Computation using QuIDDs George F. Viamontes, Manoj Rajagopalan, Igor L. Markov, and John P. Hayes Advanced Computer Architecture Laboratory University of Michigan, EECS

76. DARPA Problem Simulation of quantum computing on a classical computer Simulation of quantum computing on a classical computer Requires exponentially growing time and memory resources using standard linear algebra Requires exponentially growing time and memory resources using standard linear algebra Goal: Improve classical simulation Goal: Improve classical simulation Solution: Compress redundancy in relevant matrices and vectors Solution: Compress redundancy in relevant matrices and vectors

77. DARPA Redundancy in Quantum Computing Matrix representation of quantum gates contain block patterns Matrix representation of quantum gates contain block patterns The Tensor (Kronecker) Product The Tensor (Kronecker) Product Create state vectors and operators involving multiple qubits Create state vectors and operators involving multiple qubits Propagates block patterns in vectors and matrices Propagates block patterns in vectors and matrices

78. DARPA Example of Propagated Block Patterns Only TWO distinct blocks!

79. DARPA We could try Lempel-Ziv compression, but manipulating compressed data is difficult We could try Lempel-Ziv compression, but manipulating compressed data is difficult Try using compression based on structure that we understand, e.g., Try using compression based on structure that we understand, e.g., Complex getMatrixElement(int row, int col, int qubits) { return pow ( sqrt(2), qubits ) *( innProdMod2 ( row, col ) ? 1 : -1 ); } Complex getMatrixElement(int row, int col, int qubits) { return pow ( sqrt(2), qubits ) *( innProdMod2 ( row, col ) ? 1 : -1 ); } Still difficult do manipulate Still difficult do manipulate Consider a decision tree based on row & col Consider a decision tree based on row & col No exponential compression (?) No exponential compression (?) Compressed Representations That Capture Structure

80. DARPA *BDDs: Data Structures that Exploit Redundancy Binary Decision Diagrams (BDDs) exploit repeated sub-structure Binary Decision Diagrams (BDDs) exploit repeated sub-structure Different variants: ROBDDs, ZDDs, ADDs, FDDs, EVDDs,… Different variants: ROBDDs, ZDDs, ADDs, FDDs, EVDDs,… Common idea: bottom-up merging of nodes in decision trees Common idea: bottom-up merging of nodes in decision trees Example: f = a AND b Example: f = a AND b a f b 10 Assign value of 1 to variable x Assign value of 0 to variable x

81. DARPA *BDDs: Data Structures that Exploit Redundancy BDDs have been used to simulate classical logic circuits [Lee59, Bryant86] BDDs have been used to simulate classical logic circuits [Lee59, Bryant86] A circuit can be “simulated” on all input values at once A circuit can be “simulated” on all input values at once BDDs made useful by fast operations BDDs made useful by fast operations Bryant’s main contribution: ROBDDs Bryant’s main contribution: ROBDDs A fixed ordering of nodes + reduction rules A fixed ordering of nodes + reduction rules Potentially less compression, but faster algorithms Potentially less compression, but faster algorithms Used in most *DD data structures, including QuIDDs Used in most *DD data structures, including QuIDDs Compare to “read-once branching programs” Compare to “read-once branching programs”

82. DARPA Basic BDD Operations [Bryant1986] ( |A| = number of nodes in BDD A ) ( |A| = number of nodes in BDD A ) Most BDD operations are based on recursive procedures: ITE, Apply, etc Most BDD operations are based on recursive procedures: ITE, Apply, etc Typically take two or three BDDs as arguments Typically take two or three BDDs as arguments Apply(A,B) has space and time complexity Apply(A,B) has space and time complexity Apply is an algorithmic form of Boole’s Expansion Apply is an algorithmic form of Boole’s Expansion Different types of *DDs optimize operations for specific contexts and reduction rules, e.g., Different types of *DDs optimize operations for specific contexts and reduction rules, e.g., EVDDs (edge-valued), ZDDs (zero-suppressed), etc EVDDs (edge-valued), ZDDs (zero-suppressed), etc

83. DARPA Linear Algebra via BDDs Variants of BDDs have been used to represent matrices and vectors Variants of BDDs have been used to represent matrices and vectors Algebraic Decision Diagrams (ADDs) treat variable nodes as matrix indices [Bahar93] Algebraic Decision Diagrams (ADDs) treat variable nodes as matrix indices [Bahar93] ADDs compress repeated block patterns in matrices and vectors ADDs compress repeated block patterns in matrices and vectors Linear Algebraic operations can be performed as ADD traversals (i.e., w/o decompression) Linear Algebraic operations can be performed as ADD traversals (i.e., w/o decompression) From general to specific: From general to specific: MTBDDs  ADDs  QuIDDs MTBDDs  ADDs  QuIDDs

84. DARPA Quantum Information Decision Diagrams Quantum Information Decision Diagrams (QuIDDs) Quantum Information Decision Diagrams (QuIDDs) An application of ADDs to the quantum computing domain An application of ADDs to the quantum computing domain Similar structure to ADDs Similar structure to ADDs Three types of nodes Three types of nodes Row, Column, Terminal Row, Column, Terminal Use modified ADD operations Use modified ADD operations

85. DARPA QuIDD Structure BDD variable ordering BDD variable ordering Defines the order in which different node types appear Defines the order in which different node types appear QuIDD variable ordering interleaves row and column variables QuIDD variable ordering interleaves row and column variables Terminal nodes are always last Terminal nodes are always last

86. DARPA Quantum Circuit Simulation Issues Specific to QuIDDs Use state-vector representation Use state-vector representation In principle, QuIDDs can also model the density-matrix representation In principle, QuIDDs can also model the density-matrix representation Avoid matrix-matrix mult. (for efficiency) Avoid matrix-matrix mult. (for efficiency) Tensor products and matrix-vector multiplications are performed Tensor products and matrix-vector multiplications are performed Are very efficient Are very efficient

87. DARPA QuIDD Vectors Use column and terminal variables Use column and terminal variables Represent qubit state vectors Represent qubit state vectors Some examples: Some examples: f f 00 01 10 11 00 01 10 11 T T

88. DARPA QuIDD Matrices Use row, column, and terminal variables Use row, column, and terminal variables Represent gates / unitary matrices Represent gates / unitary matrices There is no requirement for unitary matrices, There is no requirement for unitary matrices, Constant factors can be stored separately Constant factors can be stored separately

89. DARPA Example: 2-Qubit Hadamard QuIDD f 00 01 10 11 10011100

90. DARPA Based on the Apply algorithm [Bryant1984,ClarkeEtAl1996] Based on the Apply algorithm [Bryant1984,ClarkeEtAl1996] Construct new QuIDDs by traversing two QuIDD operands Construct new QuIDDs by traversing two QuIDD operands Perform “op” at terminals (op can be *, +, etc.) Perform “op” at terminals (op can be *, +, etc.) The variable ordering directs the traversal The variable ordering directs the traversal General Form: f op g where f and g are QuIDDs, and x and y are variables in f and g, respectively General Form: f op g where f and g are QuIDDs, and x and y are variables in f and g, respectively QuIDD Operations

91. DARPA To compute A  B To compute A  B Every element of a matrix A is multiplied by the entire matrix B Every element of a matrix A is multiplied by the entire matrix B QuIDD implementation: uses Apply QuIDD implementation: uses Apply Operands are A and B Operands are A and B Variables of operand B are shifted Variables of operand B are shifted “op” is defined to be multiplication “op” is defined to be multiplication Tensor Product

92. DARPA A modified form of the Apply function A modified form of the Apply function Dot-product can be done on QuIDDs without decompression Dot-product can be done on QuIDDs without decompression “Skipped” nodes are counted “Skipped” nodes are counted A factor of 2 #skipped is multiplied by dot-products A factor of 2 #skipped is multiplied by dot-products QuIDD Implementation QuIDD Implementation Modified ADD matrix multiply algorithm [Bahar93] Modified ADD matrix multiply algorithm [Bahar93] Support complex number terminals Support complex number terminals Account for row/column variable ordering Account for row/column variable ordering Matrix Multiplication

93. DARPA Other Operations Matrix addition Matrix addition Call to Apply with “op” set to addition Call to Apply with “op” set to addition Scalar operations Scalar operations A special one-operand version of Apply A special one-operand version of Apply Qubit measurement Qubit measurement A combination of matrix multiplications, tensor products, and scalar operations A combination of matrix multiplications, tensor products, and scalar operations

94. DARPA Simulation of Grover’s Algorithm QuIDDPro was tested by running instances of Grover’s Algorithm QuIDDPro was tested by running instances of Grover’s Algorithm Results indicate linear memory usage in many cases Results indicate linear memory usage in many cases Any circuit with an oracle whose QuIDD form is polynomial in # of qubits Any circuit with an oracle whose QuIDD form is polynomial in # of qubits

95. DARPA Sample Circuit Representation H H H Oracle H H Conditional Phase Shift H H H |0> |1>..................

96. DARPA # iterations computed [BoyerEtAl96] # iterations computed [BoyerEtAl96] # iterations = # iterations = Where Where M=# of solutions, 2 q =# of elements in data set M=# of solutions, 2 q =# of elements in data set Exponential runtime on a quantum computer Exponential runtime on a quantum computer When M is small, the number of iterations is exponential in the number of qubits When M is small, the number of iterations is exponential in the number of qubits Simulation of Grover’s Algorithm

97. DARPA Projected Grover Iterations SANITY CHECK: Make sure that the number of iterations predicted by Boyer et al. results in the highest probability of measuring the item(s) to be searched SANITY CHECK: Make sure that the number of iterations predicted by Boyer et al. results in the highest probability of measuring the item(s) to be searched

98. DARPA Experiment versus Predictions

99. DARPA Simulation Results for Grover’s Algorithm Linear growth of QuIDDs in Grover’s algo Linear growth of QuIDDs in Grover’s algo Number of nodes in QuIDDs shown Number of nodes in QuIDDs shown

100. DARPA Grover’s Algorithm: Results using Oracle 1 Oracle 1 “searches” for one element in the data set Oracle 1 “searches” for one element in the data set Oracle polynomial in size Oracle polynomial in size Linear memory asymptotics Linear memory asymptotics Run-times are extremely low vs Matlab Run-times are extremely low vs Matlab

101. DARPA Grover’s Algorithm: Results using Oracle 1 Linear growth with QuIDDPro

102. DARPA Grover’s Algorithm: Results using Mod-1024 Oracle Finds elements in the data set whose 10 least significant bits are 1 Finds elements in the data set whose 10 least significant bits are 1 Useful in demonstrating asymptotics Useful in demonstrating asymptotics Memory and runtime are governed purely by the size of the system Memory and runtime are governed purely by the size of the system

103. DARPA Grover’s Algorithm: Results using Mod-1024 Oracle For data up to n=25 qubits, linear least-squares regression shows that memory (MB) grows as 7.5922 + 0.0410n For data up to n=25 qubits, linear least-squares regression shows that memory (MB) grows as 7.5922 + 0.0410n Linear growth with QuIDDPro

104. DARPA Conclusions and Future Work Asymptotic performance when QuIDD form of oracle is poly-sized Asymptotic performance when QuIDD form of oracle is poly-sized QuIDDPro : ~1.66 n ; Ideal Q. Computer : ~1.41 n QuIDDPro : ~1.66 n ; Ideal Q. Computer : ~1.41 n Far more efficient than other classical simulation techniques Far more efficient than other classical simulation techniques MATLAB, Blitz++:  (2 n ) MATLAB, Blitz++:  (2 n ) We plan to simulate other algorithms using QuiDD Pro (+ inject errors) We plan to simulate other algorithms using QuiDD Pro (+ inject errors) A simulation of Shor’s algorithm operational A simulation of Shor’s algorithm operational Details in quant-ph/0208003 Details in quant-ph/0208003

105. DARPA References [1] C.Y. Lee, “Representation of Switching Circuits by Binary Decision Diagrams”, Bell System Technical Jour., 38:985-999, 1959. [2] R. Bryant, “Graph-Based Algorithms for Boolean Function Manipulation”, IEEE Trans. On Computers, vol. C-35, pp. 677-691, Aug 1986. [3] R. I. Bahar et al., Algebraic Decision Diagrams and their Applications”, In Proc. IEEE/ACM ICCAD, pp. 188-191, 1993. [4] E. Clarke et al., “Multi-Terminal Binary Decision Diagrams and Hybrid Decision Diagrams”, In T. Sasao and M. Fujita, eds, Representations of Discrete Functions, pp. 93-108, Kluwer, 1996. [5] M. Boyer et al., “Tight Bounds on Quantum Searching”, Fourth Workshop on Physics and Computation, Boston, Nov 1996.