2 Instruction Set Architecture (ISA) The ISA is the interface between hardware and software.The ISA serves as an abstraction layer between the HW and SWSoftware doesn’t need to know how the processor is implementedAny processor that implements the ISA appears equivalentAn ISA enables processor innovation without changing softwareThis is how Intel has made billions of dollars.Before ISAs, software was re-written/re-compiled for each new machine.SoftwareProc #1ISAProc #2
3 What is instruction set architecture (ISA)? Instruction set of a computer: the portion of the computer visible to the assembly level programmer or to the compiler writer ISADefines registersDefines data transfer modes (instructions) between registers, memory and I/OThere should be sufficient instructions to efficiently translate any programNext, define instruction set format – binary representation used by the hardwareVariable-length vs. fixed-length instructions
5 Instruction Set Architectures There are 4 classes of ISAStackEmbedded processorsAccumulatorRegister-memoryPentiumRegister-Register (Load-store)Sparc
6 Instruction Set Architecture For a general purpose high-performance computerRegister-Register (Load-store) is the preferred choiceCPI uniform for most instructionsBetter pipeliningFixed length instructionsSimpler encodingThe complier is more complicated
7 Important issues to consider for designing an ISA What are the different addressing modes that should be usedWhat is the length of instructionsWhat are the different instructions usedWhat is the type and size of operands
13 Displacement and Immediate Values Important addressing modes: Register, immediate, displacement, register indirect. Account for 88% of workload.Through measurements, bits are enough to cover the majority of cases for the value of immediateThis will allow to have instruction sets of fixed size of 32 bits – most microprocessorsopcodersrt65rdshamtfuncR-Type Formatopcodersrtimmediate6516I-Type Formatopcodeimmediate626J-Type Format
14 Instruction Usage Example: Top 10 Intel X86 Instructions Rankinstructionloadconditional branchcomparestoreaddandsubmove register-registercallreturnTotalInteger Average Percent total executed122%20%16%12%8%6%5%4%1%96%2345678910Observation: Simple instructions dominate instruction usage frequency.
15 Instruction Set Encoding Considerations affecting instruction set encoding:To have as many registers and address modes as possible.The Impact of the size of the register and addressing mode fields on the average instruction size and on the average program.To encode instructions into lengths that will be easy to handle in the implementation. On a minimum to be a multiple of bytes.
16 Instruction Format Fixed Variable Hybrid Summary: Operation, address specifier 1, address specifier 2, address specifier 3.MIPS, SPARC, Power PC.VariableOperation & # of operands, address specifier1, …, specifier n.VAXHybridIntel x86operation, address specifier, address field.Operation, address specifier 1, address specifier 2, address field.Operation, address field, address specifier 1, address specifier 2.Summary:If code size is most important, use variable format.If performance is most important, use fixed format.
17 Three Examples of Instruction Set Encoding Operations &no of operandsAddressspecifier 1Addressfield 1Addressspecifier nAddressfield nVariable: VAX (1-53 bytes)OperationAddressfield 1Addressfield 2Addressfield3Fixed: DLX, MIPS, PowerPC, SPARCOperationAddressfieldAddressSpecifierAddressSpecifier 1AddressSpecifier 2OperationAddress fieldAddressSpecifierAddressfield 2OperationAddressfield 1Hybrid : IBM 360/370, Intel 80x86
18 Summary: ISAUse general purpose registers with a load-store architecture.Support these addressing modes: displacement, immediate, register indirect.Support these simple instructions: load, store, add, subtract, move register, shift, compare equal, compare not equal, branch, jump, call, return.Support these data size: 8-,16-,32-bit integer, IEEE FP standard.Provide at least 16 general purpose registers plus separate FP registers and aim for a minimal instruction set.
19 Alternative Architectures Design alternative:provide more powerful operationsgoal is to reduce number of instructions executeddanger is a slower cycle time and/or a higher CPILet’s look (briefly) at IA-32“The path toward operation complexity is thus fraught with peril. To avoid these problems, designers have moved toward simpler instructions”
20 IA - 32 1978: The Intel 8086 is announced (16 bit architecture) 1980: The 8087 floating point coprocessor is added1982: The increases address space to 24 bits, +instructions1985: The extends to 32 bits, new addressing modes: The 80486, Pentium, Pentium Pro add a few instructions (mostly designed for higher performance)1997: 57 new “MMX” instructions are added, Pentium II1999: The Pentium III added another 70 instructions (SSE)2001: Another 144 instructions (SSE2)2003: AMD extends the architecture to increase address space to 64 bits, widens all registers to 64 bits and other changes (AMD64)2004: Intel capitulates and embraces AMD64 (calls it EM64T) and adds more media extensions“This history illustrates the impact of the “golden handcuffs” of compatibility:“adding new features as someone might add clothing to a packed bag” “an architecture that is difficult to explain and impossible to love”
21 IA-32 Overview Complexity: Instructions from 1 to 17 bytes long one operand must act as both a source and destinationone operand can come from memorycomplex addressing modes e.g., “base or scaled index with 8 or 32 bit displacement”Saving grace:the most frequently used instructions are not too difficult to buildcompilers avoid the portions of the architecture that are slow“what the 80x86 lacks in style is made up in quantity, making it beautiful from the right perspective”