1. 1 Scalable Pattern Matching for High Speed Networks Authors: Christopher R.Clark and David E. Schemmel Publisher: Proceedings of IEEE Symposium on Field- Programmable Custom Computing Machines(FCCM) Present: Kia-Tso Chang Date: November 1 2007

2. Three designed method on FPGA 1. brute-force, 2. deterministic finite automata (DFA) 3. non-deterministic finite automata (NFA).

3. Distributed comparators and Character Decoder 3

4. Pattern-matching module using multi-character decoder 4

5. Four-character parallel NFA circuit for the pattern “abcde” 5

6. Upper bound of per matcher

7. Each FPGA logic element (LE) can implement up to a four-input logic gate and a flip-flop,

8. Upper bound of per matcher

10. Experiment result 10

11. Experiment result 11

12. Throughput and capacity trade- off summary 12

13. Throughput and capacity trade- off summary

14. Performance comparison with previous work