1. June 6, 2001US Japan Meeting e + e - Collider Detector R&D Status Report to US Japan Committee Daniel Marlow Princeton University June 5, 2001

2. June 6, 2001US Japan Meeting Projects and Participants Radiation hard readout for the Silicon Vertex Detectors –Hawaii, KEK, Princeton, Tokyo Resistive Plate Chamber R&D –KEK, Oregon, Princeton, SLAC, Tohoku Vertex Detector R&D –Hawaii, KEK, Tokyo

3. June 6, 2001US Japan Meeting The SVD Readout Chip: the VA1 128 channels Descendent of Viking (O. Toker et al., NIM A340 (1994) 572.) AMS 1.2 um CMOS Noise:

4. June 6, 2001US Japan Meeting New Directions Incorporation of a fast trigger output. Implementation in a sub-micron CMOS process to attain radiation hardness.

5. June 6, 2001US Japan Meeting Radiation Damage in MOS Transistors depends on ionization Reducing the oxide thickness by half is equivalent to cutting the dose by four.

6. June 6, 2001US Japan Meeting Process Comparison In the range of interest to BELLE, the noise vs. dose performance dramatically improves with decreasing feature size, as expected.

7. June 6, 2001US Japan Meeting Indeed, the 0.35-um process exhibits phenomenal radiation hardness.

8. June 6, 2001US Japan Meeting Single Event Phenomena Although the submicron processes appear to offer a total dose resistance that is considerably better than needed, one still needs to worry about “upsets” induced by ionization that is highly localized in space and time. This is our current focus.

9. June 6, 2001US Japan Meeting Single Event Upset and Latch-up Single event upset (SEU) –Flip-flops flip when they should flop. Single event latch-up (SELU) –Parasitic conduction paths form in the IC’s substrate. –Current draws large enough to destroy the chip through Joule heating can occur. It is not clear how these effects will vary with feature size. Experimental measurements are needed.

10. June 6, 2001US Japan Meeting SELU Mitigation According to the AMS measurements, the addition of an epitaxial layer during fabrication should improve the latchup performance of the VA1 chips. We are refabricating the VA1 chip in the AMS 0.35 um CMOS with an epitaxial layer added.

11. June 6, 2001US Japan Meeting SEU Mitigation The logic design of the VA1TA will incorporate 2 of 3 majority logic to detect and automatically correct SEU-induced errors.

12. June 6, 2001US Japan Meeting SEU, SELU, and the VA1 Despite these precautions, it is important that we understand the effects. We thus plan to carry out systematic comparisons between VA1’s implemented with varying line widths (and with & without an epitaxial layer). IDEAS has submited two major engineering runs: –VA1 to AMS 0.35  m with epitaxial layer. –VA1TA to AMS 0.35  m with epitaxial layer.

13. June 6, 2001US Japan Meeting RPC Principles of Operation A passing charged particle induces an avalanche, which develops into a spark. The discharge is quenched when all of the locally ( ) available charge is consumed. Spacers Signal pickup (x) India Ink Resistive plates 8 kV Signal pickup (y) India Ink +++++++++++++++ _ _ _ _ _ _ _ _ _ _ _ +++ +++++ _ _ _ _ _ _ _ The discharged area recharges slowly through the high-resistivity glass plates. Before After

14. June 6, 2001US Japan Meeting RPCs are not robust. Dark currents arising from surface defects can cause a loss of efficiency. In the early days of Belle, serious efficiency losses were observed. Fortunately, these problems were resolved, but similar problems continue to plague the BaBar RPCs. Belle

15. June 6, 2001US Japan Meeting The RPC Death Spiral High dark currents induce a IR voltage drop across the resistive plates, which lowers the voltage across the gap, causing the chamber to slide off the efficiency plateau. Increasing the applied voltage doesn’t help since it merely results in increased dark current.

16. June 6, 2001US Japan Meeting Surface Defects in the Babar RPCs Work by J. Va’vra and H. Band of BaBar has shown that the linseed oil surfaces have suffered damage.

17. June 6, 2001US Japan Meeting Irreversible Current Increases Due to Stalagmite Formation

18. June 6, 2001US Japan Meeting Resistivity of Linseed Oil It appears that the linseed oil is not fully polymerized, which leaves it with a low resistance. Data from C. Lu (Princeton/BaBar)

19. June 6, 2001US Japan Meeting Oxygen Treatment C. Lu at Princeton (BaBar) found that oxygen causes the linseed oil to polymerize, which raises its resistivity and lowers the dark current. Before 5 days N 2 /O 2 15 days N 2 /O 2 Data from C. Lu (Princeton/BaBar)

20. June 6, 2001US Japan Meeting Is Oxygen a Long-Term Cure? Efficiency vs. Time RegionBefore Treatment After 5 days dry air 8 days later 8 days dry air 7 days later 29 days later Worst Area 83.1%94.0%89.7%96.0%88.5%82.3% Best Area 90.6%95.4%94.7%94.0% 95.0% Full- chamber Average 83.9%93.6%90.7%95.5%92.0%90.5% Data from C. Lu (Princeton). Obtained using RPC extracted from BaBar.

21. June 6, 2001US Japan Meeting Pixel Detector R&D Areas of study include bump-bonding studies & electronics development. Original vendor list included GEC Marconi (Britain) and Advanced Interconnect Technology (AIT Hong Kong). Marconi withdrew, so that bumps were pursued with AIT. Test samples were 20 x 40 arrays of 50 x 100 µm 2 pixels. Both “thick” (300 µm) and “thin” (100 µm) sensors were bonded to dummy readout chips were bonded.

22. June 6, 2001US Japan Meeting Sample Test Bonds Optical Image SEM Image

23. June 6, 2001US Japan Meeting IR Images Good bonds Overpressed bonds IR images were used to examine the bonds, instead of the x-ray technique used by ATLAS. To our knowledge, this is the first time that 100 µm- thick wafers have been successfully bump bonded in HEP.

24. June 6, 2001US Japan Meeting Summary Development of SVD radiation-hard electronics is proceeding smoothly. RPC studies are showing some interesting effects, but a clear solution to the bakelite RPC efficiency- loss problem is not fully in hand. There are some promising results on thin-pixel detector bump bonding, but much remains to be done.