1. Exploring Latency Constraints of Co-Processing Boards Grant Jenks UCLA

2.  Original Plan ◦ What I had planned to do.  Accomplishments ◦ What I actually did.  Problems ◦ What happened.  Revised Plan ◦ What’s the new plan.

3.  Analyze and Synthesize ◦ First quarter: Analysis  Develop the test platform.  Test the different classes of programs on the platform and collect a lot of data. ◦ Second quarter: Synthesis  From the data, determine that “sweet spot.”  Based on analysis, determine a way to validate the initial tests using existing hardware or FPGAs.  If validation simply cannot happen then more fully develop why this is so.

4.  Vtune Tests ◦ Dozens of different processor loads recorded.  This data can demonstrate a strong need for another processor.  Classic PTLsim Tests (32-bit) ◦ Dozens of different programs with various parameters were run to determine optimal performance in a one processor and one program environment.  This data can demonstrate the optimal performance of a program with no contention for memory or processing. ◦ Analyzed code and evaluated how to change it so that the proper simulation environment can be created.  Full Simulation PTLsim/XEN (64-bit) ◦ Modified kernel code and patched kernels to allow for PTLsim enhancements. ◦ Gained lots of experience in systems administration tasks and operating system’s practicals. ◦ Tried dozens of different configurations trying to get this to work.

5.  Hardware Issues ◦ Haven’t been able to acquire a 64-bit computer with virtualization technology support. ◦ SATA Hard Drive failed in test machine.  PTLsim/XEN ◦ Code is difficult to change. ◦ Systems work requires tons of time while juggling operating systems. ◦ XEN technologies are still fairly new and not well supported. ◦ Little help in general with XEN technologies.  Vtune ◦ Reproducibility is sometimes challenging.  Bad Luck ◦ Nothing works “out-of-the-box”  Scripts have been tweaked to make builds and runs work properly.

6.  Produce working simulation environment under PTLsim/XEN.  Run a wide variety of tests in the simulation environment under different hardware scenarios. ◦ The goal is to get at least five different software scenarios tested under at least five different hardware simulations.  Determine the “sweet spot” for a hardware implementation of a co-processing board. ◦ Go back and run more tests in Classic PTLsim or Vtune if necessary.  Time permitting, validate “sweet spot” hardware implementation with real-world co-processing board.

7.  Original plan did not properly estimate the time it would take to set up the simulation environment.  Data collected can establish the need for more processing power and show optimal program execution.  There’s a lot of momentum going into the second quarter but it is questionable whether the tests can be verified.