1. Slide 1 Instructor: Dr. Hong Jiang Department of Computer Science & Engineering University of Nebraska-Lincoln Classroom: 108 Avery Hall; Time: 1:30pm-2:20pm, M.W.F. Office Hour: 12:30am-1:20pm, M.W.F.; Office: 268 Avery jiang@cse.unl.edu Cse.unl.edu/~jiang/cs432 CSCE432/832 High Performance Processor Architecture Fall 2007

2. Slide 2 Course Syllabus Description: CSCE432/832 Course Title: High-Performance Processor Architectures; Credit Hours(3 cr); Prereqisites: CSCE 430, MATH 314, and MATH 380 or ELEC 410; or permission; Description: This course addresses high performance computing in the context of the state of the art processor architectures, including the underlying principles and micro-architectures of contemporary high performance processors. It assumes basic knowledge of pipelined scalar processors, and covers the Superscalar, Multi-core/Many-core, and Very Long Instruction Word (VLJW) architectural paradigms. Concepts of virtual machine architecture will also be discussed. Numerous case studies of actual systems highlight real-world design trade-offs and amplify the theoretical discussions. Course Schedule: An overview and tentative (and approximate) schedule : Main Topics to Be CoveredReadings RequiredLecture Time Scalar Processor DesignChapters 1 & 22 weeks Superscalar OrganizationChapter 31-2 weeks Superscalar Techniques & CasesChapter 4-73-4 weeks Multicore ProcessorsReferences provided3-4 weeks Advanced Techniques for MulticoreChapters 8-9 + Ref. book3-4 weeks

3. Slide 3 Course Syllabus (cont.) Grading Policy: Pre-requisite exam will be given on the Monday of the third week, with preparation materials provided during the first two weeks. One Exam will be given during the course. Course Project dealing with aspects of design and analysis of multicore processors 3-4 homework assignments will be given. Each is due in class on its specified due date. Late work is penalized 20% per day. Once solutions are published, late work cannot be accepted for credit. While collaboration on homework is permitted, blatant copying will not be tolerated. Violators, if caught, will subject to penalties ranging from a zero for the homework assignment in question to an F grade for the course, depending on the severity of the violation. Final Grade will be generated according to the weight associated with each component listed below: Pre-requisite Test: 5%; Homework Assignment:25%; Exam:30%; Course Project: 40%; Textbook: John P. Shen and Mikko H. Lipasti, Modern Processor Design - Fundamentals of Superscalar Processors, McGraw-Hill Higher Education, 2005. Reference Book & Materials: John L. Hennessy and David A. Patterson, Computer Architecture -- A Quantitative Approach, 4th Edition, Morgan Kaufmann Publishers Inc., 2007. And Latest literature in the related areas.