1. Week 6.1Spring 2006 14:332:331 Computer Architecture and Assembly Language Spring 2006 Week 6 VHDL Programming [Adapted from Dave Patterson’s UCB CS152 slides and Mary Jane Irwin’s PSU CSE331 slides]

2. Week 6.2Spring 2006 Motivation for Process Construct  How would you build the logic (and the VHDL code) for a 32 by 2 multiplexor given inverters and 2 input nands? 1 0 SEL A DOUT B

3. Week 6.3Spring 2006 MUX CSA Description 1 0 SEL A DOUT B  How can we describe the circuit in VHDL if we don’t know what primitive gates we will be designing with? entity MUX32X2 is port(A,B: in std_logic_vector(31 downto 0); DOUT: out std_logic_vector(31 downto 0); SEL: in std_logic); end MUX32X2;

4. Week 6.4Spring 2006 Mux Process Description  Process fires whenever a signal in the “sensitivity list” changes entity MUX32X2 is port(A,B: in std_logic_vector(31 downto 0); DOUT: out std_logic_vector(31 downto 0); SEL: in std_logic); end MUX32X2; architecture process_behavior of MUX32X2 is begin mux32x2_process: process(A, B, SEL) begin if (SEL = ‘0’) then DOUT <= A after 5 ns; else DOUT <= B after 4 ns; end if; end process mux32x2_process; end process_behavior; 1 0 SEL A DOUT B

5. Week 6.5Spring 2006 VHDL Process Features  Process body is executed sequentially to completion in zero (simulation) time  Delays are associated only with assignment of values to signals l marked by CSAs <= operator  Variable assignments take effect immediately l marked by := operator  Upon initialization all processes are executed once  After initialization processes are data-driven l activated by events on signals in sensitivity list l waiting for the occurrence of specific events using wait statements

6. Week 6.6Spring 2006 Process Programming Constructs  if-then-else l Boolean valued expressions are evaluated sequentially until first true is encountered  case l branches must cover all possible values for the case expression  for loop l loop index declared (locally) by virtue of use in loop stmt l loop index cannot be assigned a value or altered in loop body  while loop l condition may involve variables modified within the loop while (condition) loop for index in value1 to value2 loop case (expression) is when ‘value0’ =>... end case; if (expression1 = ‘value1’) then... elsif (expression2 = ‘value2’) then... end if;

7. Week 6.7Spring 2006 Behavioral Description of a Register File library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity regfile is port(write_data: in std_logic_vector(31 downto 0); dst_addr,src1_addr,src2_addr: in UNSIGNED(4 downto 0); write_cntrl: in std_logic; src1_data,src2_data: out std_logic_vector(31 downto 0)); end regfile; Register File src1_addr src2_addr dst_addr write_data 32 bits src1_data src2_data 32 words write_cntrl

8. Week 6.8Spring 2006 Behavioral Description of a Register File, con’t architecture process_behavior of regfile is type reg_array is array(0 to 31) of std_logic_vector (31 downto 0); begin regfile_process: process(src1_addr,src2_addr,write_cntrl) variable data_array: reg_array := ( (X”00000000”),... (X”00000000”)); variable addrofsrc1, addrofsrc2, addrofdst: integer; begin addrofsrc1 := conv_integer(src1_addr); addrofsrc2 := conv_integer(src2_addr); addrofdst := conv_integer(dst_addr); if write_cntrl = ‘1’ then data_array(addrofdst) := write_data; end if; src1_data <= data_array(addrofsrc1) after 10 ns; src2_data <= data_array(addrofsrc2) after 10 ns; end process regfile_process; end process_behavior;

9. Week 6.9Spring 2006 Process Construct with Wait Statement library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity dff is port(D,clk: in std_logic; Q,Qbar: out std_logic); end dff; architecture dff_behavior of dff is begin output: process begin wait until (clk’event and clk = ‘1’); Q <= D after 5 ns; Qbar <= not D after 5 ns; end process output; end dff_behavior; D Q clk Qbar positive edge-triggered dff

10. Week 6.10Spring 2006 Wait Statement Types  Wait statements specify conditions under which a process may resume execution after suspension l wait for time expression -suspends process for a period of time defined by the time expression l wait on signal -suspends process until an event occurs on one (or more) of the signals l wait until condition -suspends process until condition evaluates to specified Boolean l wait  Process resumes execution at the first statement following the wait statement wait until (clk’event and clk = ‘1’); wait for (20 ns); wait on clk, reset, status;

11. Week 6.11Spring 2006 Signal Attributes Function attributeFunction signal_name’event Boolean value signifying a change in value on this signal signal_name’active Boolean value singifying an assignment made to this signal (may not be a new value!) signal_name’last_event Time since the last event on this signal signal_name’last_active Time since the signal was last active signal_name’last_value Previous value of this signal  Attributes are used to return various types of information about a signal

12. Week 6.12Spring 2006 Things to Remember About Processes  A process must have either a sensitivity list or at least one wait statement  A process cannot have both a sensitivity list and a wait statement  Remember, all processes are executed once when the simulation is started  Don’t confuse signals and variables. l Signals are declared either in the port definitions in the entity description or as internal signals in the architecture description. They are used in CSAs. Signals will be updated only after the next simulation cycle. l Variable exist only inside architecture process descriptions. They are used in variable assignment statements. Variables are updated immediately.

13. Week 6.13Spring 2006 Finite State Machine “Structure” D(0) Q(0) a clk b z comb dff D(1) Q(1) Fetch PC = PC+4 DecodeExec

14. Week 6.14Spring 2006 Structural VHDL Model in1 Qbar(0) clk in2 out1  System is described by its component interconnections l assumes we have previously designed entity-architecture descriptions for both comb and dff with behavioral models comb c_state(1)nxt_state(1) b a z clk D(0) Q(0) dff D(1) Q(1) Qbar(1) nxt_state(0)c_state(0)

15. Week 6.15Spring 2006 Finite State Machine Structural VHDL entity seq_circuit is port(in1,in2,clk: in std_logic; out1: out std_logic); end seq_circuit; architecture structural of seq_ circuit is component comb port(a,b: in std_logic; z: out std_logic; c_state: in std_logic_vector (1 downto 0); nxt_state: out std_logic_vector (1 downto 0)); end component; component dff port(D,clk: in std_logic; Q,Qbar: out std_logic); end component; for all: comb use entity work.comb(comb_behavior); for all: dff use entity work.dff(dff_behavior); signal s1,s2: std_logic_vector (1 downto 0); begin C0:comb port map(a=>in1,b=>in2,c_state=>s1,z=>out1, nxt_state=>s2); D0:dffport map(D=>s2(0),clk=>clk,Q=>s1(0),Qbar=>open); D1:dffport map(D=>s2(1),clk=>clk,Q=>s1(1),Qbar=>open); end structural;

16. Week 6.16Spring 2006 Summary  Introduction to VHDL l A language to describe hardware -entity = symbol, architecture ~ schematic, signals = wires l Inherently concurrent (parallel) l Has time as concept l Behavioral descriptions of a component -can be specified using CSAs -can be specified using one or more processes and sequential statements l Structural descriptions of a system are specified in terms of its interconnections -behavioral models of each component must be provided