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Exemple dexécution dun programme ISTORE 1 Jeux dinstructions de la machine Traduction en hexa 0x36 0x01.

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Exemple chargement dune instruction 3 0x00 0xXX 0x05 0x00 0x04 Addr Alu JM 4 to 16 Decoder High Bit C B MPC B Bus C Bus Memory control signals.

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Presentation on theme: "Exemple dexécution dun programme ISTORE 1 Jeux dinstructions de la machine Traduction en hexa 0x36 0x01."— Presentation transcript:

1 Exemple dexécution dun programme ISTORE 1 Jeux dinstructions de la machine Traduction en hexa 0x36 0x01

2 Exemple chargement dune instruction 3 0x00 0x36 0x05 0x00 0x04 Addr Alu JM 4 to 16 Decoder High Bit C B MPC B Bus C Bus Memory control signals (rd,wr,fetch) N Z MIR JMPC JAMN/JAMZ

3 Exemple Istore (H=LV; Goto Istore2) 3 0x01 0x36 0x05 0x00 0x04 Addr Alu JM 4 to 16 Decoder High Bit C B MPC B Bus C Bus Memory control signals (rd,wr,fetch) N Z MIR JMPC JAMN/JAMZ

4 Exemple Istore (MAR=MBRU+H; Goto Istore3) 3 0x01 0x05 0x00 0x04 0x00 Addr Alu JM 4 to 16 Decoder High Bit C B MPC B Bus C Bus Memory control signals (rd,wr,fetch) N Z MIR JMPC JAMN/JAMZ Arrivée de la donnée. (Lecture déclenchée dans le Main1)

5 Exemple Istore (MDR=TOS;Wr; Goto Istore4) 3 0x01 0x05 0x00 0x04 Addr Alu JM 4 to 16 Decoder High Bit C B MPC B Bus C Bus Memory control signals (rd,wr,fetch) N Z MIR JMPC JAMN/JAMZ

6 Exemple Istore (MDR=TOS;Wr; Goto Istore4) 3 0x01 0x04 0x01 0x05 0x00 0x04 Addr Alu JM 4 to 16 Decoder High Bit C B MPC B Bus C Bus Memory control signals (rd,wr,fetch) N Z MIR JMPC JAMN/JAMZ

7 Exemple Istore (PC=PC+1;fetch; Goto Istore6) 3 0x04 0x01 0x04 0x00 0x04 Addr Alu JM 4 to 16 Decoder High Bit C B MPC B Bus C Bus Memory control signals (rd,wr,fetch) N Z MIR JMPC JAMN/JAMZ

8 Exemple Istore (TOS=MDR; Goto Main1) 3 0x04 0x07 0x02 0x01 0x04 0x00 0x04 Addr Alu JM 4 to 16 Decoder High Bit C B MPC B Bus C Bus Memory control signals (rd,wr,fetch) N Z MIR JMPC JAMN/JAMZ Arrivée de la donnée. Lecture déclenchée dans Istore4

9 Résultat 3 0x04 0x07 0x02 0xXX 0x04 0x00 0x07 Addr Alu JM 4 to 16 Decoder High Bit C B MPC B Bus C Bus Memory control signals (rd,wr,fetch) N Z MIR JMPC JAMN/JAMZ Arrivée de la prochaine instruction.


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